Self-boost, source following, and sample-and-hold for accessing memory cells

ABSTRACT

Methods, systems, and devices for operating a memory cell or cells are described. A capacitor coupled with an access line may be precharged and then boosted such that the charge stored in the capacitor is elevated to a higher voltage with respect to a memory cell. The boosted charge in the capacitor may support sensing operations that would otherwise require a relatively higher voltage. Some embodiments may employ charge amplification between an access line and a sense component, which may amplify signals between the memory cell and the sense component, and reduce charge sharing between these components. Some embodiments may employ “sample-and-hold” operations, which may re-use certain components of a sense component to separately generate a signal and a reference, reducing sensitivity to manufacturing and/or operational tolerances. In some embodiments, sensing may be further improved by employing “self-reference” operations that use a memory cell to generate its own reference.

BACKGROUND

The following relates generally to memory systems and more specificallyto self-boost, source following, and sample-and-hold for accessingmemory cells.

Memory devices are widely used to store information in variouselectronic devices such as computers, wireless communication devices,cameras, digital displays, and the like. Information is stored byprogramming different states of a memory device. For example, binarymemory devices have two logic states, often denoted by a logic “1” or alogic “0.” In other memory devices, more than two logic states may bestored. To access the stored information, a component of the electronicdevice may read, or sense, the stored logic state in the memory device.To store information, a component of the electronic device may write, orprogram, the logic state in the memory device.

Various types of memory devices exist, including those that employmagnetic hard disks, random access memory (RAM), read only memory (ROM),dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM(FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phasechange memory (PCM), and others. Memory devices may be volatile ornon-volatile. Non-volatile memory, such as PCM and FeRAM, may maintainstored logic states for extended periods of time even in the absence ofan external power source. Volatile memory devices, such as DRAM, maylose stored logic states over time unless they are periodicallyrefreshed by a power source. In some cases non-volatile memory may usesimilar device architectures as volatile memory but may havenon-volatile properties by employing such physical phenomena asferroelectric capacitance or different material phases.

Improving memory devices, may include increasing memory cell density,increasing read/write speeds, increasing reliability, increasing dataretention, reducing power consumption, or reducing manufacturing costs,among other metrics. In some cases, operation of a memory device mayrequire a relatively high voltage for sensing and/or writing operations,and the components associated with providing the relatively high voltagemay be associated with relatively high power consumption or requirerelatively greater electrical insulation. Furthermore, a memory devicemay employ substantially duplicated components to provide a signal and areference, and manufacturing and/or operational tolerances of theduplicated components may introduce an imbalance between the signal andthe reference that can lead to sensing difficulties.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example memory device that may support self-boost,source following, and sample-and-hold for accessing memory cells inaccordance with various embodiments of the present disclosure.

FIG. 2 illustrates an example circuit that may support self-boost,source following, and sample-and-hold for accessing memory cells inaccordance with various embodiments of the present disclosure.

FIG. 3 illustrates an example of non-linear electrical properties withhysteresis plots for a memory cell that may support self-boost, sourcefollowing, and sample-and-hold for accessing memory cells in accordancewith various embodiments of the present disclosure.

FIG. 4 illustrates an example of a circuit that may support self-boostand sample-and-hold for accessing memory cells in accordance withvarious embodiments of the present disclosure.

FIG. 5 shows a timing diagram illustrating operations of an exampleaccess procedure that may support self-boost for accessing memory cellsin accordance with various embodiments of the present disclosure.

FIG. 6 illustrates an example of a circuit that may support self-boost,source following, and sense-and-hold for accessing memory cells inaccordance with various embodiments of the present disclosure.

FIG. 7 shows a timing diagram illustrating operations of an exampleaccess procedure that may support self-boost and source following foraccessing memory cells in accordance with various embodiments of thepresent disclosure.

FIG. 8 illustrates an example of a circuit that may support self-boost,source following, and sense-and-hold for accessing memory cells inaccordance with various embodiments of the present disclosure.

FIG. 9 shows a timing diagram illustrating operations of an exampleaccess procedure that may support self-boost, source following, andsample-and-hold for accessing memory cells in accordance with variousembodiments of the present disclosure.

FIG. 10 shows a timing diagram illustrating operations of an exampleaccess procedure that may support self-boost, source following, and aself-referencing sample-and-hold for accessing memory cells inaccordance with various embodiments of the present disclosure.

FIG. 11 shows a block diagram of a memory device that may supportself-boost, source following, and sample-and-hold for accessing memorycells in accordance with various embodiments of the present disclosure.

FIG. 12 shows a block diagram of a memory controller that may supportself-boost, source following, and sample-and-hold for accessing memorycells in accordance with various embodiments of the present disclosure.

FIG. 13 shows a diagram of a system including a device that may supportself-boost, source following, and sample-and-hold for accessing memorycells in accordance with various embodiments of the present disclosure.

FIG. 14 shows a flowchart illustrating a method that may supportself-boost, source following, and sample-and-hold for accessing memorycells in accordance with various embodiments of the present disclosure.

FIG. 15 shows a flowchart illustrating a method that may supportsample-and-hold for accessing memory cells in accordance with variousembodiments of the present disclosure.

DETAILED DESCRIPTION

The described features and operations generally relate to memorysystems, and in particular to various combinations of self-boost, sourcefollowing, and sample-and-hold features and operations for accessing amemory cell.

In some memory systems, accessing a memory cell may benefit from using arelatively high supply voltage. However, providing a relatively highvoltage may be associated with correspondingly high power consumption,complex components, large devices, or high insulation requirements,relative to power consumption, complexity, size, and insulation employedwith lower supply voltages. Thus, it may be preferable to supportaccessing a memory cell with relatively lower voltage devices.

In accordance with embodiments of the present disclosure, a capacitorcoupled with an access line of a sense component may be precharged witha relatively low voltage difference, and then boosted with a relativelylow voltage such that the charge stored in the capacitor is elevated toa relatively high voltage with respect to the memory cell (e.g.,boosting a terminal of the capacitor to a relatively high voltage). Suchoperations may be referred to as “self-boost.” The boosted charge in thecapacitor may support sensing operations that would otherwise require arelatively high voltage from a single voltage supply of the memorysystem, and/or would take a relatively longer time when using arelatively low voltage supply. For example, the boosted charge in such acapacitor may facilitate sensing schemes for a ferroelectric memory cellthat reverse a saturation polarization of certain logic states in such amemory cell.

In some memory systems that include capacitors coupled with an accessline of a sense component, it may be preferable to use relatively lowcapacitance (e.g., relatively low capacitance integrator capacitors)such that a voltage signal resulting from a flow of charge of a memorycell is relatively high. However, such systems may require relativelysmall and/or sensitive components in a sense component. Thus, in somememory systems it may be beneficial to employ charge amplificationbetween an access line and a sense component in accordance withembodiments of the present disclosure, which may be referred to as“source following.” Source following may amplify signals between thememory cell and the sense component, and may also isolate the memorycell from the sense component thereby preventing charge sharing betweenthese components. The charge amplification may also support largercomponents in the sense component, which may improve robustness of thememory system.

Some memory systems may apply self-boost and/or source following forboth a signal line and a reference line coupled with a sense component,which may support relatively fast sense operations because certainoperations of developing a signal and developing a reference may occurconcurrently. Such memory systems may use substantially duplicatedcomponents for supporting self-boost and/or source following operations.The substantially duplicated components may have different properties,such as threshold voltage (e.g., for transistors) and/or insulationproperties, as a result of manufacturing and/or operational tolerances.Although the relatively fast sense operations supported by theduplicated components may be suitable for some applications, it may bebeneficial in some applications to improve robustness to manufacturingand/or operational tolerances despite a drawback of relatively sloweroperations. Thus, some memory systems may employ “sample-and-hold”operations in accordance with embodiments of the present disclosure,which may re-use certain components of a sense component to separatelygenerate a signal and a reference, thereby reducing sensitivity tomanufacturing and/or operational tolerances.

In some memory systems that support sample-and-hold operations, sensingmay be further improved by employing “self-reference” operations inaccordance with embodiments of the present disclosure. For example, amemory cell may be sensed a first time, with the resulting signallatched and stored at a first terminal of a sense component. The samememory cell may be sensed a second time, with the resulting signallatched and stored at a second terminal of the sense component. Thesignals stored at the terminals of the sense component may be comparedin order to determine a logic state originally stored in the memorycell. For example, as applied to a ferroelectric memory cell,self-reference operations using a positive sense voltage used to sense apositively polarized memory cell may store a displacement signal at boththe first terminal and second terminal of the sense component. On theother hand, self-reference operations using a positive sense voltageused to sense a negatively polarized memory cell may store adisplacement and polarization signal at the first terminal of the sensecomponent, and a displacement signal at the second terminal of the sensecomponent. The difference, or lack thereof, between the first and secondsensing of the same memory cell may be used to determine the logic stateoriginally stored in the memory cell, and because the same memory cellis accessed for both a sense signal and a reference signal, effects dueto circuit path resistance, intrinsic capacitance, and the like may becancelled between the first and second sensing. Accordingly, some memorysystems may employ self-reference operations when increased robustnessto circuit variations are beneficial.

Features of the disclosure introduced above are further described belowin the context of a memory array. Specific examples are then describedfor self-boost, source following, sample-and-hold, and self-referenceoperations. These and other features of the disclosure are furtherillustrated by and described with reference to apparatus diagrams,system diagrams, and flowcharts that relate to self-boost, sourcefollowing, sample-and-hold, and self-reference for accessing a memorycell.

FIG. 1 illustrates an example memory device 100 that may supportself-boost, source following, and sample-and-hold for accessing a memorycell in accordance with various embodiments of the present disclosure.Memory device 100 may also be referred to as an electronic memoryapparatus. Memory device 100 includes memory cells 105 that areprogrammable to store different logic states. In some cases a memorycell 105 may be programmable to store two logic states, denoted a logic0 and a logic 1. In some cases, a memory cell 105 may be programmable tostore more than two logic states.

In some examples a memory cell 105 may store an electrical chargerepresentative of the programmable logic states in a capacitive memoryelement. For example, a charged and uncharged capacitor of a memory cell105 may represent two logic states, respectively, or a positivelycharged and a negatively charged capacitor of a memory cell 105 mayrepresent two logic states, respectively. DRAM architectures may usesuch designs, and the capacitor employed may include a dielectricmaterial with linear or para-electric electric polarization propertiesas the insulator. In some examples, such as FeRAM, a memory cell 105 mayinclude a ferroelectric capacitor having a ferroelectric material as aninsulating layer between terminals of the capacitor. Different levels ofpolarization of a ferroelectric capacitor may represent different logicstates. Ferroelectric materials have non-linear polarization propertiesincluding those discussed in further detail with reference to FIG. 3.

Memory device 100 may include a three-dimensional (3D) memory array,where a plurality of two-dimensional (2D) memory arrays (e.g., decks)are formed on top of one another. This may increase the number of memorycells 105 that may be placed or created on a single die or substrate ascompared with 2D arrays, which in turn may reduce production costs orincrease the performance of the memory device 100, or both. The decksmay be separated by an electrically insulating material. Each deck maybe aligned or positioned so that memory cells 105 may be approximatelyaligned with one another across each deck, forming a stack of memorycells 105.

According to the example of FIG. 1, each row of memory cells 105 iscoupled with one of a plurality of first access lines 110 (e.g., a wordline (WL)), and each column of memory cells 105 is coupled with one of aplurality of second access lines 115 (e.g., a digit line (DL)). Thus,one memory cell 105 may be located at the intersection of one of thefirst access lines 110 and one of the second access lines 115. Thisintersection may be referred to as an address of the memory cell 105.References to word lines and bit lines, or their analogues, areinterchangeable without loss of understanding or operation. In somecases, first access lines 110 and second access lines 115 may besubstantially perpendicular to one another in the memory device 100(e.g., when viewing a plane of a deck of the memory device 100, as shownin FIG. 1). Although the access lines described with reference to FIG. 1are shown as simple lines between memory cells 105 and coupledcomponents, access lines may include other circuit elements, such ascapacitors, resistors, transistors, amplifiers, and others, which may beused to support sensing operations including those described herein.

In some architectures, the logic storing component (e.g., a capacitivememory element) of a memory cell 105 may be electrically isolated from asecond access line 115 by a selection component. A first access line 110may be coupled with and may control the selection component. Forexample, the selection component may be a transistor and the firstaccess line 110 may be coupled with a gate of the transistor. Activatingthe first access line 110 may result in an electrical connection orclosed circuit between the logic storing component of the memory cell105 and its corresponding second access line 115. The second access line115 may then be accessed to read and/or write the memory cell 105.

In some examples, memory cells 105 may also be coupled with one of aplurality of third access lines 120 (e.g., a plate line (PL)). In someexamples the plurality of third access lines may couple memory cells 105with a voltage source for various sensing and/or writing operationsincluding those described herein. For example, when memory cells 105employ a capacitor for storing a logic state, a second access line 115may provide access to a first terminal of the capacitor, and a thirdaccess line 120 may provide access to a second terminal of thecapacitor. As used herein, the term “terminal” need not suggest aphysical boundary or connection point of a capacitor of a memory cell105, or any other circuit element. Rather, “terminal” may refer to areference point of a circuit relevant to the circuit element, which mayalso be referred to as a “node” or “reference point.” Although theplurality of third access lines 120 of the memory device 100 are shownas substantially parallel with the plurality of second access lines 115,in other examples a plurality of third access lines 120 may besubstantially parallel with the plurality of first access lines 110, orin any other configuration.

Operations such as reading, writing, and rewriting may be performed on amemory cell 105 by activating or selecting a first access line 110, asecond access line 115, and/or a third access line 120 coupled with thememory cell 105, which may include applying a voltage, a charge, and/ora current to the respective access line. Access lines 110, 115, and 120may be made of conductive materials, such as metals (e.g., copper (Cu),silver (Ag), aluminum (Al), gold (Au), tungsten (W), titanium (Ti),etc.), metal alloys, carbon, or other conductive materials, alloys, orcompounds. Upon selecting a memory cell 105, a resulting signal may beused to determine the stored logic state. For example, a memory cell 105with a capacitive memory element storing a logic state may be selected,and the resulting flow of charge via an access line and/or resultingvoltage of an access line may be detected to determine the programmedlogic state of the memory cell 105.

Accessing memory cells 105 may be controlled through a row decoder 125and a column decoder 135. For example, a row decoder 125 may receive arow address from the memory controller 150 and activate the appropriatefirst access line 110 based on the received row address. Similarly, acolumn decoder 135 may receive a column address from the memorycontroller 150 and activate the appropriate second access line 115.Thus, in some examples a memory cell 105 may be accessed by activating afirst access line 110 and a second access line 115.

Upon accessing, a memory cell 105 may be read, or sensed, by a sensecomponent 130. For example, sense component 130 may be configured todetermine the stored logic state of a memory cell 105 based on a signalgenerated by accessing the memory cell 105. The signal may include avoltage, an electrical charge, an electrical current, or a combinationthereof, and sense component 130 may include voltage sense amplifiers,charge sense amplifiers, current sense amplifiers, or both. For example,a voltage may be applied to a memory cell 105 having a capacitive memoryelement (e.g., using the corresponding first access line 110, secondaccess line 115, and/or third access line 120), and a magnitude of theresulting flow of charge and/or voltage may depend on the stored chargeand/or polarization of the capacitive memory element.

Sense component 130 may include various transistors or amplifiers usedto detect and amplify a signal, which may be referred to as latching.The detected logic state of a memory cell 105 may then be output via aninput/output component 140. In some cases, sense component 130 may be apart of column decoder 135 or row decoder 125. In some cases, sensecomponent 130 may be coupled with or in electronic communication withcolumn decoder 135, row decoder 125, and/or memory controller 150.

A memory cell 105 may also be set, or written, by activating therelevant first access line 110, second access line 115, and/or thirdaccess line 120—i.e., a logic state may be stored in the memory cell105. Column decoder 135 or row decoder 125 may accept data, for examplevia input/output component 140, to be written to the memory cells 105.In the case of a capacitive memory element, a memory cell 105 may bewritten by applying a voltage to the capacitor, and then isolating thecapacitor (e.g., isolating the capacitor from a voltage source used towrite the memory cell 105). In the case of ferroelectric memory, aferroelectric memory element (e.g., a ferroelectric capacitor) of amemory cell 105 may written by applying a voltage with a magnitude highenough to polarize the ferroelectric memory element (e.g., applying asaturation voltage), and the ferroelectric memory element may beisolated (e.g., floating), or a zero net voltage may be applied acrossthe ferroelectric memory element (e.g., grounding or virtually groundingthe ferroelectric memory element).

In some memory architectures, accessing the memory cell 105 may degradeor destroy the stored logic state. Thus, re-write or refresh operationsmay be performed to return a programmed logic state to memory cell 105after such accessing. In DRAM, for example, a logic-storing capacitor ofa memory cell 105 may be partially or completely discharged during asense operation, corrupting the stored logic state. So the logic statemay be re-written after a sense operation. In some examples, activatinga single access line (e.g., a first access line 110, a second accessline 115, or a third access line 120) may result in the discharge of allmemory cells 105 along that access line. Thus, in some examples allmemory cells 105 in a row or column may need to be re-written after anaccess operation. But when accessing a memory cell 105 havingnon-volatile properties (e.g., a FeRAM memory cell), accessing thememory cell 105 may not destroy the logic state and, thus, the memorycell 105 may not require re-writing after accessing.

Some memory architectures, including DRAM, may lose their stored logicstates over time unless they are periodically refreshed (e.g., by anvoltage source external to the memory cells 105). For example, a chargedcapacitor may become discharged over time through leakage currents,resulting in the loss of the stored charge. The refresh rate of suchmemory devices may be relatively high, e.g., tens of refresh operationsper second for DRAM, which may result in significant power consumption.With increasingly larger memory arrays, such power consumption mayinhibit the deployment or operation of memory arrays (e.g., powersupplies, heat generation, material limits, etc.), especially fordevices that rely on a finite source of energy, such as a battery.Memory cells 105 having memory elements with non-volatile properties mayresult in improved performance relative to other memory architectures.For example, FeRAM may offer comparable read/write speeds as DRAM butmay have non-volatile properties that allow for reduced powerconsumption and/or increased cell density.

The memory controller 150 may control the operation (read, write,re-write, refresh, self-boost, source following, sample-and-hold, etc.)of memory cells 105 through the various components, for example,initiating operations of and/or receiving information from the rowdecoder 125, column decoder 135, and sense component 130, and otherscomponents as described herein. In some cases, one or more row decoder125, one or more column decoder 135, one or more sense component 130,and/or one or more input/output component 140 may be co-located with thememory controller 150. Memory controller 150 may generate row and columnaddress signals in order to activate a desired first access line 110,second access line 115, and/or third access line 120. Furthermore, one,multiple, or all memory cells 105 within memory device 100 may beaccessed simultaneously. For example, multiple or all memory cells 105of memory device 100 may be accessed simultaneously during a resetoperation in which all memory cells 105, or a group of memory cells 105,are set to a single logic state

Memory controller 150 may also generate and/or control application ofvarious voltages, charges, or currents used during the operation of thememory device 100 (e.g., via various voltage supplies, charge supplies,current supplies, ground points, virtual ground points, etc.). Theamplitude, shape, or duration of an applied voltage, charge, or currentdiscussed herein may be adjusted or varied and may be different for thevarious operations discussed in operating memory device 100. The memorycontroller 150 may also generate and/or control application of variouslogic signals (e.g., via various voltage supplies, logic controllers,etc.), which may control various switching components in accordance withembodiments of the present disclosure.

FIG. 2 illustrates an example circuit 200 that may support self-boost,source following, and sample-and-hold for accessing memory cells inaccordance with various embodiments of the present disclosure. Circuit200 includes a memory cell 105-a and a sense component 130-a, which maybe examples of a memory cell 105 and a sense component 130 describedwith reference to FIG. 1. Circuit 200 may also include a word line 205,a digit line 210, and a plate line 215, which in some examples maycorrespond to a first access line 110, a second access line 115, and athird access line 120, respectively, as described with reference toFIG. 1. The circuit 200 may also include a reference line 270 used bythe sense component 130-a to determine a stored logic state of thememory cell 105-a. However, in various examples other configurations ofaccess lines and/or reference lines are possible.

Memory cell 105-a may include a logic storage component (e.g., a memoryelement), such as capacitor 220 that has a first plate, cell plate 230,and a second plate, cell bottom 240. Cell plate 230 and cell bottom 240may be capacitively coupled through a dielectric material positionedbetween them (e.g., in a DRAM application), or capacitively coupledthrough a ferroelectric material positioned between them (e.g., in aFeRAM application). The orientation of cell plate 230 and cell bottom240 may be flipped without changing the operation of memory cell 105-a.Cell plate 230 may be accessed via plate line 215 and cell bottom 240may be accessed via digit line 210. As described herein, various statesmay be stored by charging, discharging, and/or polarizing the capacitor220.

Capacitor 220 may be in electronic communication with digit line 210,and the stored logic state of capacitor 220 may be read or sensed byoperating various elements represented in circuit 200. For example, thememory cell 105-a may also include a selection component 250, and thecapacitor 220 can be coupled with digit line 210 when selectioncomponent 250 is activated, and the capacitor 220 can be isolated fromdigit line 210 when selection component 250 is deactivated. Activatingselection component 250 may be referred to as selecting memory cell105-a, and deactivating selection component 250 may be referred to asdeselecting memory cell 105-a. In some cases, selection component 250 isa transistor and its operation is controlled by applying a voltage tothe transistor gate, where the voltage applied across the transistor(e.g., the voltage between the transistor gate terminal and thetransistor source terminal) for activating the transistor is greaterthan the threshold voltage magnitude of the transistor. The word line205 may be used to activate the selection component 250. For example, aselection voltage applied to the word line 205 (e.g., a word line logicsignal) may be applied to the gate of a transistor of selectioncomponent 250, which may connect capacitor 220 with the digit line 210(e.g., providing a conductive path between the capacitor 220 and thedigit line 210.

In other examples, the positions of the selection component 250 and thecapacitor 220 in the memory cell 105-a may be switched, such thatselection component 250 is coupled between plate line 215 and cell plate230, and the capacitor 220 is coupled between digit line 210 and theother terminal of selection component 250. In such an embodiment, theselection component 250 may remain in electronic communication withdigit line 210 through capacitor 220. This configuration may beassociated with alternative timing and biasing for read and writeoperations.

In examples that employ a ferroelectric capacitor 220, the capacitor 220may not fully discharge upon connection to digit line 210. In variousschemes, to sense the logic state stored by a ferroelectric capacitor220, a voltage may be applied to plate line 215 and/or digit line 210,and the word line 205 may be biased to select memory cell 105-a. In somecases, the plate line 215 and/or digit line 210 may be virtuallygrounded and then isolated from the virtual ground, which may bereferred to as a floating condition, prior activating the word line 205.Operation of the memory cell 105-a by varying the voltage to cell plate230 (e.g., via the plate line 215) may be referred to as “moving cellplate.” Biasing the plate line 215 and/or digit line 210 may result in avoltage difference (e.g., the voltage of the plate line 215 minus thevoltage of the digit line 210) across the capacitor 220. The voltagedifference may accompany a change in the stored charge on capacitor 220,where the magnitude of the change in stored charge may depend on theinitial state of capacitor 220—e.g., whether the initial logic statestored a logic 1 or a logic 0. In some schemes the change in the storedcharge of the capacitor may cause a change in the voltage of the digitline 210, which may be used by the sense component 130-a to determinethe stored logic state of the memory cell 105-a.

Digit line 210 may connect many memory cells 105, and the digit line 210may have a length that results in a non-negligible intrinsic capacitance260 (e.g., on the order of picofarads (pF)), which may couple the digitline with a voltage source 265-a, which may represent a common ground orvirtual ground voltage, or the voltage of an adjacent access line of thecircuit 200 (not shown). Although illustrated as a separate component inFIG. 2, the intrinsic capacitance 260 may be associated with propertiesdistributed throughout the digit line 210. For example, the intrinsiccapacitance may depend on physical characteristics of the digit line210, including conductor dimensions (e.g., length, width, and/orthickness) of the digit line 210. Further, additional capacitors may becoupled with an access line including the digit line 210, such as one ormore integrator capacitors that support various sensing and writingoperations, including those described herein that support self-boostoperations. Thus, a change in voltage of digit line 210 after selectingthe memory cell 105-a may depend on the net capacitance of the digitline 210. That is, as charge flows through the digit line 210, somefinite charge may be stored in the digit line 210 (e.g., in theintrinsic capacitance 260 or any other capacitance coupled with thedigit line 210), and the resulting voltage of the digit line 210 maydepend on the net capacitance of the digit line 210. The resultingvoltage of digit line 210 after selecting the memory cell 105-a may becompared to a reference (e.g., a voltage of reference line 270) by thesense component 130-a in order to determine the logic state that wasstored in the memory cell 105-a. Other operations may be used to supportselecting and/or sensing the memory cell 105-a, including operations forself-boost, source following, sample-and-hold, and self-referenceoperations as described herein.

In some examples, the circuit 200 may include an amplifier 275, whichmay amplify signals of the digit line 210 prior to a sensing operation.The amplifier 275 may include, for example, a transistor, a cascode, orany other charge or voltage amplifier. In such examples, a line betweenthe sense component 130-a and the amplifier 275 may be referred to asignal line (e.g., signal line 280). In examples without an amplifier275, the digit line 210 may connect directly with the sense component130-a. Although the digit line 210 and the signal line 280 areidentified as separate lines, the digit line 210, the signal line 280,and any other lines connecting a memory cell 105 with a sense component130 may be referred to as a single access line in accordance with thepresent disclosure. Constituent portions of such an access line may beidentified separately for the purposes of illustrating interveningcomponents, and intervening signals, in various example configurations.

Sense component 130-a may include various transistors or amplifiers todetect and amplify a difference in signals, which may be referred to aslatching. For example, sense component 130-a may include a senseamplifier that receives and compares the voltage of digit line 210(e.g., as stored or latched at a first terminal 131-a) with a referencevoltage of the reference line 270 (e.g., as stored or latched at asecond terminal 132-a). An output of the sense amplifier may be drivento a higher (e.g., a positive) or a lower (e.g., negative or ground)voltage based on the comparison at the sense amplifier. For instance, ifthe digit line 210 (or signal line 280, where applicable) coupled withthe sense component 130-a has a lower voltage than the reference line270, the output of the sense component 130-a may be driven to arelatively lower voltage of a first sense component voltage source 265-b(e.g., a voltage of V₁, which may be a ground voltage substantiallyequal to V₀, or a negative voltage, for example). The sense component130-a may latch the output of the sense amplifier to determine the logicstate stored in the memory cell 105-a (e.g., detecting a logic 0 whenthe digit line 210 has a lower voltage than the reference line 270. Ifthe digit line 210 (or signal line 280, where applicable) coupled withthe sense component 130-a has a higher voltage than the reference line270, the output of the sense component 130-a may be driven to thevoltage of a second sense component voltage source 265-c (e.g., avoltage of V₂). The sense component 130-a may latch the output of thesense amplifier to determine the logic state stored in the memory cell105-a (e.g., detecting a logic 1 when the digit line 210 has a highervoltage than the reference line 270). The latched output of theamplifier, corresponding to the detected logic state of memory cell105-a, may then be output via an input/output (I/O) line 290 (e.g.,through a column decoder 135 via input/output component 140 describedwith reference to FIG. 1).

To perform a write operation on the memory cell 105-a, a voltage may beapplied across the capacitor 220. Various methods may be used. In oneexample, the selection component 250 may be activated through the wordline 205 in order to electrically connect the capacitor 220 to the digitline 210. A voltage may be applied across capacitor 220 by controllingthe voltage of cell plate 230 (e.g., through plate line 215) and cellbottom 240 (e.g., through digit line 210). For example, to write a logic0, cell plate 230 may be taken high (e.g., applying a positive voltageto plate line 215), and cell bottom 240 may be taken low (e.g.,virtually grounding or applying a negative voltage to digit line 210).The opposite process may be performed to write a logic 1, where cellplate 230 is taken low and cell bottom 240 is taken high. In some casesthe voltage applied across the capacitor 220 during a write operationmay have a magnitude equal to or greater than a saturation voltage of aferroelectric material in the capacitor 220, such that the capacitor 220is polarized, and thus maintains a charge even when the magnitude ofapplied voltage is reduced, or if a zero net voltage is applied acrossthe capacitor 220.

FIG. 3 illustrates an example of non-linear electrical properties withhysteresis plots 300-a and 300-b for a memory cell 105 that may supportself-boost, source following, and sample-and-hold for accessing memorycells in accordance with various embodiments of the present disclosure.Hysteresis plots 300-a and 300-b may illustrate an example writingprocess and reading process, respectively, for a memory cell 105employing a ferroelectric capacitor 220 as described with reference toFIG. 2. Hysteresis plots 300-a and 300-b depict the charge, Q, stored onthe ferroelectric capacitor 220 as a function of a voltage difference,V, between the terminals of the ferroelectric capacitor 220 (e.g., whencharge is permitted to flow into or out of the ferroelectric capacitor220 according to the voltage difference, V).

A ferroelectric material is characterized by a spontaneous electricpolarization, where the material may maintain a non-zero electric chargein the absence of an electric field. Example ferroelectric materialsinclude barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconiumtitanate (PZT), and strontium bismuth tantalate (SBT). Ferroelectriccapacitors 220 described herein may include these or other ferroelectricmaterials. Electric polarization within a ferroelectric capacitor 220results in a net charge at the surface of the ferroelectric material,and attracts opposite charge through the terminals of the ferroelectriccapacitor 220. Thus, charge is stored at the interface of theferroelectric material and the capacitor terminals. Because the electricpolarization may be maintained in the absence of an externally appliedelectric field for relatively long times, even indefinitely, chargeleakage may be significantly decreased as compared with, for example,capacitors without ferroelectric properties such as those used inconventional DRAM arrays. Employing ferroelectric materials may reducethe need to perform refresh operations as described above for some DRAMarchitectures.

Hysteresis plots 300-a and 300-b may be understood from the perspectiveof a single terminal of a ferroelectric capacitor 220. By way ofexample, if the ferroelectric material has a negative polarization,positive charge accumulates at the associated terminal of theferroelectric capacitor 220. Likewise, if the ferroelectric material hasa positive polarization, a negative charge accumulates at the associatedterminal of the ferroelectric capacitor 220. Additionally, it should beunderstood that the voltages in hysteresis plots 300-a and 300-brepresent a voltage difference across the capacitor (e.g., between theterminals of the ferroelectric capacitor 220) and are directional. Forexample, a positive voltage may be realized by applying a positivevoltage to the perspective terminal (e.g., a cell bottom 240) andmaintaining the reference terminal (e.g., a cell plate 230) at ground orvirtual ground (or approximately zero volts (0V)). In some examples anegative voltage may be applied by maintaining the perspective terminalat ground and applying a positive voltage to the reference terminal. Inother words, positive voltages may be applied to arrive at a negativevoltage difference across the ferroelectric capacitor 220 and therebynegatively polarize the terminal in question. Similarly, two positivevoltages, two negative voltages, or any combination of positive andnegative voltages may be applied to the appropriate capacitor terminalsto generate the voltage difference shown in hysteresis plots 300-a and300-b.

As depicted in hysteresis plot 300-a, a ferroelectric material used in aferroelectric capacitor 220 may maintain a positive or negativepolarization when there is no net voltage difference between theterminals of the ferroelectric capacitor 220. For example, thehysteresis plot 300-a illustrates two possible polarization states,charge state 305-a and charge state 310-b, which may represent apositively saturated polarization state and a negatively saturatedpolarization state, respectively. Charge states 305-a and 310-a may beat a physical condition illustrating remnant polarization (Pr) values,which may refer to the polarization (or charge) that remains uponremoving the external bias (e.g., voltage). The coercive voltage is thevoltage at which the charge (or polarization) is zero. According to theexample of hysteresis plot 300-a, charge state 305-a may represent alogic 1 when no voltage difference is applied to the ferroelectriccapacitor 220, and charge state 310-a may represent a logic 0 when novoltage difference is applied to the ferroelectric capacitor 220. Insome examples, the logic values of the respective charge states may bereversed to accommodate other schemes for operating a memory cell 105.

A logic 0 or 1 may be written to the memory cell by controlling theelectric polarization of the ferroelectric material, and thus the chargeon the capacitor terminals, by applying a net voltage difference acrossthe ferroelectric capacitor 220. For example, voltage 315 may be avoltage equal to or greater than a positive saturation voltage, andapplying the voltage 315 across the ferroelectric capacitor 220 mayresult in charge accumulation until charge state 305-b is reached (e.g.,writing a logic 1). Upon removing the voltage 315 from the ferroelectriccapacitor 220 (e.g., applying a zero net voltage across the terminals ofthe ferroelectric capacitor 220), the charge state of the ferroelectriccapacitor 220 may follow the path 320 shown between charge state 305-band the charge state 305-a at zero voltage. Similarly, voltage 325 maybe a voltage equal to or lesser than a negative saturation voltage, andapplying the voltage 325 across the ferroelectric capacitor 220 resultsin charge accumulation until charge state 310-b is reached (e.g.,writing a logic 0). Upon removing the voltage 325 from the ferroelectriccapacitor 220 (e.g., applying a zero net voltage across the terminals ofthe ferroelectric capacitor 220), the charge state of the ferroelectriccapacitor 220 may follow the path 330 shown between charge state 310-band the charge state 310-a at zero voltage. In some examples the voltage315 and the voltage 325, representing saturation voltages, may have thesame magnitude, but opposite polarity.

To read, or sense, the stored state of a ferroelectric capacitor 220, avoltage may be applied across the ferroelectric capacitor 220. Inresponse to the applied voltage, the subsequent charge Q stored by theferroelectric capacitor changes, and the degree of the change may dependon the initial polarization state. In other words, the resulting chargeQ may depend on whether charge state 305-a or 310-a was initiallystored. For example, hysteresis plot 300-b illustrates the reading ofstored charge states 305-a and 310-a. A read voltage 335 may be applied,for example, as a voltage difference via a digit line 210 and a plateline 215 as discussed with reference to FIG. 2. The read voltage 335 maybe applied across the ferroelectric capacitor 220 when a memory cell 105is selected (e.g., by activating a selection component 250 as describedwith reference to FIG. 2). Upon applying the read voltage 335 to theferroelectric capacitor 220, charge may flow into or out of theferroelectric capacitor 220 via the digit line 210 and plate line 215,and different charge states may result depending on whether theferroelectric capacitor 220 was at charge state 305-a (e.g., a logic 1)or at charge state 310-a (e.g., a logic 0). Although read voltage 335 isshown as a positive voltage across the ferroelectric capacitor 220, inalternative operations a read voltage may be a negative voltage acrossthe ferroelectric capacitor 220.

When performing a read operation on a ferroelectric capacitor 220 at thecharge state 305-a (e.g., a logic 1), additional positive charge mayaccumulate across the ferroelectric capacitor 220, and the charge statemay follow path 340 until reaching the charge and voltage of chargestate 305-b. Such a read operation may not change the remnantpolarization of the ferroelectric capacitor 220 that stored charge state305-a, and thus after performing the read operation the ferroelectriccapacitor 220 may return to charge state 305-a when the read voltage 335is removed (e.g., by applying a zero net voltage across theferroelectric capacitor 220). Thus, performing a read operation with apositive read voltage on a ferroelectric capacitor 220 with a chargestate 305-a may be considered a non-destructive read process.

When performing the read operation on the ferroelectric capacitor 220 atthe charge state 310-a (e.g., a logic 0), the stored charge may reversepolarity as a net positive charge accumulates across the ferroelectriccapacitor 220, and the charge state may follow path 360 until reachingthe charge and voltage of charge state 310-b. In various examples, aread operation with a positive read voltage (e.g., read voltage 335) mayresult in a reduction or a reversal of remnant polarization of thecapacitor 220 that stored charge state 310-a. In other words, accordingto the properties of the ferroelectric material, after performing theread operation the ferroelectric capacitor 220 may not return to chargestate 310-a when the read voltage 335 is removed (e.g., by applying azero net voltage across the capacitor 220). Rather, when applying a zeronet voltage across the ferroelectric capacitor 220 after a readoperation with read voltage 335, the charge state may follow path 365from charge state 310-b to charge state 310-c, illustrating a netreduction in polarization magnitude (i.e., a less negatively polarizedcharge state than initial charge state 310-a). Thus, performing a readoperation with a positive read voltage on a ferroelectric capacitor 220with a charge state 310-a may be a destructive read process. However, insome sensing schemes, a reduced remnant polarization may still be readas the same stored logic state as a saturated remnant polarization state(e.g., supporting detection of a logic 0 from both charge state 310-aand charge state 310-c), thereby providing a degree of non-volatilityfor a memory cell 105 with respect to read operations.

The transition from charge state 310-a to charge state 310-c may beillustrative of a sensing operation that is associated with a partialreduction and/or partial reversal in polarization of a ferroelectriccapacitor 220 of a memory cell (e.g., a reduction in the magnitude ofcharge Q from charge state 310-a to charge state 310-c). In variousexamples, the amount of change in polarization of a ferroelectriccapacitor 220 of a memory cell 105 as a result of a sensing operationmay be selected according to a particular sensing scheme. In someexamples sensing operations having a greater change in polarization of aferroelectric capacitor 220 of a memory cell 105 may be associated withrelatively greater robustness in detecting a logic state of a memorycell 105. In some sensing schemes, sensing a logic 0 of a ferroelectriccapacitor 220 at a charge state 310-a may result in a full reversal ofpolarization, with the ferroelectric capacitor 220 transitioning fromcharge state 310-a to 305-a after the sensing operation. Such sensingschemes may be referred to as a “2Pr” sensing scheme, because thesensing operations may be based on a transition of charge equal to twotimes the magnitude saturation polarization of a ferroelectric capacitor220 of the memory cell 105 being sensed.

The position of charge states 305-b and charge state 310-b afterinitiating a read operation may depend on a number of factors, includingthe specific sensing scheme and circuitry. In some cases, the finalcharge may depend on the net capacitance of the digit line 210 coupledwith the memory cell 105, which may include an intrinsic capacitance260, integrator capacitors, and the like. For example, if aferroelectric capacitor 220 is electrically coupled with the digit line210 and voltage 335 is applied to the digit line, the voltage of thedigit line 210 may drop when the memory cell 105 is selected due tocharge flowing from the net capacitance of the digit line 210 to theferroelectric capacitor 220 and the. Thus, a voltage measured at a sensecomponent 130 may not be equal to the read voltage 335 and instead maydepend on the voltage of the digit line 210 following a period of chargesharing. The position of charge states 305-b and 310-b on hysteresisplot 300 upon initiating a read operation may depend on the netcapacitance of the digit line 210 and may be determined through aload-line analysis—i.e., charge states 305-b and 310-b may be definedwith respect to the net capacitance of the digit line 210. As a result,the voltage of the ferroelectric capacitor 220 after initiating a readoperation (e.g., voltage 350 when reading the ferroelectric capacitor220 that stored charge state 305-a, or voltage 355 when reading theferroelectric capacitor 220 that stored charge state 310-a), may bedifferent and may depend on the initial state of the ferroelectriccapacitor 220.

The initial state of the ferroelectric capacitor 220 may be determinedby comparing the resultant voltage of a digit line 210 (or signal line280, where applicable) with a reference voltage (e.g., via a referenceline 270 as described with reference to FIG. 2). In some examples thedigit line voltage may be the final voltage across the ferroelectriccapacitor 220 (e.g., voltage 350 when reading the ferroelectriccapacitor 220 having a stored charge state 305-a, or voltage 355 whenreading the ferroelectric capacitor 220 having a stored charge state310-a). In some examples the digit line voltage may be the differencebetween voltage 335 and the final voltage across the capacitor 220(e.g., (voltage 335-voltage 350) when reading the ferroelectriccapacitor 220 having a stored charge state 305-a, or (voltage335-voltage 355) when reading the ferroelectric capacitor 220 having astored charge state 310-a).

In some sensing schemes a reference voltage may be generated such thatthe reference voltage is between the possible resultant voltages whenreading different logic states. For example, a reference voltage may beselected to be lower than the resulting digit line voltage when readinga logic 1, and higher than the resulting digit line voltage when readinga logic 0. When reading a signal voltage across a ferroelectriccapacitor 220 of a memory cell 105, for example, the reference voltagemay be an average of voltage 350 and voltage 355. During comparison bythe sense component 130, the sensed digit line voltage may be determinedto be higher or lower than the reference voltage, and the stored logicstate of the memory cell 105 (i.e., a logic 0 or 1) may thus bedetermined.

FIG. 4 illustrates an example of a circuit 400 that may supportself-boost and sample-and-hold for accessing memory cells in accordancewith various embodiments of the present disclosure. The circuit 400includes a sense component 130-b for sensing a logic state of a memorycell 105-b. Electrical signals may be communicated between the sensecomponent 130-b and the memory cell 105-b via a digit line 210-a and asignal line 280-a, which may, in combination, be referred to as a singleaccess line of the memory cell 105-b. Signals of the access line may beillustrated by voltage V_(DL) on the digit line 210-a, and V_(sig) onthe signal line 280-a, as shown. The example circuit 400 may include anamplifier 275-a coupled between the digit line 210-a and the signal line280-a, which may be enabled by voltage source 410-1. The circuit 400 mayalso include a word line 205-a for selecting or deselecting the memorycell 105-b (e.g., by way of logic signal WL) and a reference line 270-afor providing a reference signal (e.g., V_(ref), as shown) forcomparison with a signal of the signal line 280-a when detecting a logicstate of the memory cell 105-b. The circuit 400 may also include a plateline 215-a for accessing a cell plate of a capacitor of the memory cell105-b. Thus, the memory cell 105-b may represent a memory cell coupledbetween a first access line (e.g., the digit line 210-a and the signalline 280-a) and a second access line (e.g., the word line 205-a).

The circuit 400 may include a variety of voltage sources 410, which maybe coupled with various voltage supplies and/or common grounding orvirtual grounding points of a memory device that includes the examplecircuit 400.

A voltage source 410-a may represent a common grounding point (e.g., achassis ground, a neutral point, etc.), which may be associated with acommon reference voltage having a voltage V₀, from which other voltagesare defined. The voltage source 410-a may be coupled with the digit line210-a via the intrinsic capacitance 260-a of the digit line 210-a.

A voltage source 410-b having a voltage V₁ may represent a plate linevoltage source, and may be coupled with the memory cell 105-b via aplate line 215-a of the memory cell 105-b. In some examples the voltagesource 410-b may be used for write operations, including thoseoperations described with reference to hysteresis plot 300-a of FIG. 3.

A voltage source 410-c having a voltage V₂ may represent a digit linevoltage source, and may be coupled with the digit line 210-a via aswitching component 420-a, which may be activated or deactivated by alogical signal SW₁.

A voltage source 410-d having a voltage V₃ may represent a signal lineprecharge voltage source, and may be coupled with the signal line 280-avia a switching component 420-c, which may be activated or deactivatedby a logical signal SW₃.

A voltage source 410-e having a voltage V₄ may represent a referencesignal voltage source, and may be coupled with the reference line 270-avia a switching component 420-f, which may be activated or deactivatedby a logical signal SW₆.

A voltage source 410-1 having a voltage V₁₁ may represent a digit linevoltage source, and may be coupled with an amplifier 275-a which may bean example of the amplifier 275 described with reference to FIG. 2. Forexample, the amplifier 275-a may be a transistor, and the voltage source410-1 may be coupled with the gate of the transistor. The amplifier275-a may be coupled with the signal line 280-a at a first terminal, andthe digit line 210-a at a second terminal. The amplifier 275-a mayprovide a conversion of signals between the digit line 210-a and thesignal line 280-a. For example, the amplifier 275-a may permit a flow ofcharge (e.g., electrical current) from the signal line 280-a to thedigit line 210-a, as fed or enabled by the voltage source 410-1, upon areduction in voltage of the digit line 210-a (e.g., upon selection ofthe memory cell 105-b). A relatively small flow of charge to the digitline 210-a may be associated with a relatively small change in voltageof the signal line 280-a, whereas a relatively large flow of charge tothe digit line 210-a may be associated with a relatively large change involtage of the signal line 280-a. According to the net capacitance ofthe signal line 280-a, for example, the signal line 280-a may undergo arelatively small change in voltage or a relatively large change involtage depending on the flow of charge across the amplifier 275-a afterselecting the memory cell 105-b. In some examples the amplifier 275-amay be isolated from the digit line 210-a by a switching component420-b, which may be activated or deactivated by a logical signal SW₂.The amplifier 275-a may also referred to as a “voltage regulator” or a“bias component,” relating to how the amplifier 275-a regulates a flowof charge in response to the voltage of the digit line 210-a.

The circuit may also include a first integrator capacitor 430-a and asecond integrator capacitor 430-b, which may each be coupled with arespective variable voltage source 450. For example, the firstintegrator capacitor 430-a may be coupled with the signal line 280-a ata first terminal 431-a, and coupled with a variable voltage source 450-aat a second terminal 432-a. The second integrator capacitor 430-b may becoupled with the reference line 270-a at a first terminal 431-b, andcoupled with a variable voltage source 450-b at a second terminal 432-b

In the example of circuit 400, the variable voltage source 450-a mayinclude a voltage source 410-f having a voltage V₅ and a voltage source410-g having a voltage V₆, which may be selected for connection with thefirst integrator capacitor 430-a by a switching component 420-d by wayof a logical signal SW₄. In some examples the voltage source 410-f maybe coupled with a common grounding point (not shown). In other examplesthe voltage source 410-f may be coupled with a voltage supply thatprovides a positive or negative voltage. Voltage source 410-g may becoupled with a voltage supply having a higher voltage than that ofvoltage source 410-f, thereby providing the boosting functions asdescribed herein (e.g., in accordance with the difference in voltagebetween voltage source 410-g and 410-f, equal to V₆−V₅, or simply V₆when the voltage source 410-f is grounded).

In the example of circuit 400, the variable voltage source 450-b mayinclude a voltage source 410-h having a voltage V₇ and a voltage source410-i having a voltage V₈, which may be selected for connection with thesecond integrator capacitor 430-b by a switching component 420-e by wayof a logical signal SW₅. In some examples the voltage source 410-h maybe coupled with a common grounding point (not shown). In other examplesthe voltage source 410-h may be coupled with a voltage supply thatprovides a positive or negative voltage. Voltage source 410-i may becoupled with a voltage supply having a higher voltage than that ofvoltage source 410-h, thereby providing the boosting functions asdescribed herein (e.g., in accordance with the difference in voltagebetween voltage source 410-i and 410-h, equal to V₈−V₇, or simply V₈when the voltage source 410-h is grounded).

Although circuit 400 is shown as including two variable voltage sources450, some configurations in accordance with the present disclosure mayinclude a single, common variable voltage source 450. For example, afirst voltage source 410 of a common variable voltage source 450 may becoupled with both the second terminal 432-a of the first integratorcapacitor 430-a and the second terminal 432-b of the second integratorcapacitor 430-b when a switching component 420 of the common variablevoltage source 450 is deactivated, and a second voltage source 410 ofthe common variable voltage source 450 may be coupled with both thesecond terminal 432-a of the first integrator capacitor 430-a and thesecond terminal 432-b of the second integrator capacitor 430-b when theselection component 420 of the common variable voltage source 450 isactivated. In some examples that use a common variable voltage source450, the source voltage provided to the second terminal 432-a of thefirst integrator capacitor 430-a may be different to the source voltageprovided to the second terminal 432-b of the second integrator capacitor430-b due to differences in the circuit (e.g., conductor length, width,resistance, capacitance, etc.) between the variable voltage source 450and each of the integrator capacitors 430.

Further, although the variable voltage source 450 is illustrated asincluding two voltage sources 410 and a selection component 420, avariable voltage source 450 supporting the operations herein may includeother configurations, such as a voltage buffer that provides a variablevoltage to one or both of the second terminal 432-a of the firstintegrator capacitor 430-a and the second terminal 432-b of the secondintegrator capacitor 430-b.

To support various operations described herein, the sense component130-b may be isolated from portions of the circuit 400. For example, thesense component 130-b may be coupled with the signal line 280-a via aswitching component 420-g (e.g., an isolation component), which may beactivated or deactivated by a logical signal ISO₁. Additionally oralternatively, the sense component 130-b may be coupled with thereference line 270-a via a switching component 420-h (e.g., an isolationcomponent), which may be activated or deactivated by a logical signalISO₂. Further, the sense component 130-b may be coupled with a voltagesource 410-j having a voltage V₉ and a voltage source 410-k having avoltage of V₁₀, which may be examples of sense component voltage sources256-b and 265-c, described with reference to FIG. 2, respectively.

Each of the logical signals illustrated in circuit 400 may be providedby a memory controller (not shown), such as a memory controller 150described with reference to FIG. 1. In some examples, certain logicalsignals may be provided by other components. For example, logical signalWL may be provided by a row decoder (not shown), such as a row decoder125 described with reference to FIG. 1.

In various examples, voltage sources 410 may be coupled with differentconfigurations of voltage supplies and/or common grounding or virtualgrounding points of a memory device that includes the example circuit400. For example, in some embodiments voltage sources 410-a, 410-f,410-h, or 410-j, or any combination thereof, may be coupled with thesame ground point or virtual ground point, and may provide substantiallythe same reference voltage for various operations of accessing thememory cell 105-b. In some embodiments, several voltage sources 410 maybe coupled with the same voltage supply of a memory device. For example,in some embodiments, voltage sources 410-c, 410-d, 410-g, 410-i, or410-k, or any combination thereof, may be coupled with a voltage supplyhaving a certain voltage (e.g., a voltage of 1.5V, which may be referredto as “VARY”). In such embodiments, the signal line 280-a may be boostedto a voltage substantially equal to 2*VARY, or approximately 3.0V, priorto selecting the memory cell 105-b via word line 205-a for sensing.Thus, in accordance with embodiments of the present disclosure,self-boost operations may overcome a need to provide a relatively highervoltage supply for sense operations (e.g., a voltage source of 3.0V ormore, which in some applications may refer to a “positive pump” voltageof V_(pp)). In other examples, voltage sources 410-g and 410-i may becoupled with a different voltage supply than other voltage supplies(e.g., a voltage of 1.2V, which may be referred to as “PDS”), which maythus be associated with a voltage boost of 1.2V.

In some examples the voltage sources 410-j and 410-k may be selectedaccording to particular input/output parameters. For example, voltagesources 410-j and 410-k may be substantially at 0V and 1V, respectively,in accordance with certain input/output component conventions such ascertain DRAM conventions. Although voltage sources 410 may be coupledwith common voltage supplies and/or grounding points, the voltage ofeach of the voltage sources 410 coupled with a common voltage supply orcommon grounding point may be different due to various differences inthe circuit (e.g., conductor length, width, resistance, capacitance,etc.) between the respective voltage sources 410 and the associatedcommon voltage supply or common grounding point.

Voltage source 410-e may provide a reference voltage for sensing thelogic state of the memory cell 105-b, such that V₄ is an average voltagebetween signal line voltage associated with sensing a logic 1 and alogic 0. In some examples, a voltage of V₄ may be provided as a voltagedropped from a voltage supply of the memory device, which may be thesame voltage supply coupled with other voltage sources 410. For example,V₄ may be provided by connecting voltage source 410-e with a samevoltage supply as voltage source 410-d, but with an interveningelectrical load (e.g., a resistive load or capacitance) between thevoltage supply and the voltage source 410-e).

FIG. 5 shows a timing diagram 500 illustrating operations of an exampleaccess procedure that may support self-boost for accessing memory cellsin accordance with various embodiments of the present disclosure. Theexample access procedure is described with reference to components ofthe example circuit 400 described with reference to FIG. 4.

In the example of timing diagram 500, voltage sources 410-a, 410-f and410-h are considered to be grounded, and therefore at a zero voltage(e.g., V₀=0V, V₅=0V, and V₇=0V). However, in other examples voltagesources 410-a, 410-f, and 410-h may be at non-zero voltages, and thevoltages of timing diagram 500 may thus be adjusted accordingly. In someexamples, prior to initiating the operations of timing diagram 500, thedigit line 210-a and the plate line 215-a may be controlled to the samevoltage, which may minimize charge leakage across the memory cell 105-b.For example, according to the timing diagram 500, the digit line 210-ahas an initial voltage of 0V, which may be the same as the initialvoltage of the plate line 215-a. In other examples, the digit line 210-aand the plate line 215-a may have some other initial voltage differentfrom the ground voltage.

At 501, the access procedure may include activating switching component420-c (e.g., by activating logical signal SW₃). Activating switchingcomponent 420-c may connect voltage source 410-d with the signal line280-a, and accordingly the voltage of signal line 280-a may rise tovoltage level V₃ as charge flows into the integrator capacitor 430-a.Thus, activating switching component 420-c may initiate a prechargingoperation for the integrator capacitor 430-a. For example, at 501 theswitching component 420-d may be deactivated, such that the voltagesource 410-f (e.g., a ground or virtual ground voltage at 0V) is coupledwith the second terminal 432-a of the integrator capacitor 430-a, andthe voltage source 410-d is coupled with the first terminal 431-a of theintegrator capacitor 430-a. Thus, the integrator capacitor 430-a may becharged according to the voltage difference between the voltage source410-d and the voltage source 410-f.

At 502, the access procedure may include activating switching component420-f (e.g., by activating logical signal SW₆). Activating switchingcomponent 420-f may connect voltage source 410-e with the reference line270-a, and accordingly the voltage of reference line 270-a may rise tovoltage level V₄ as charge flows into the integrator capacitor 430-b.Thus, activating switching component 420-f may initiate a prechargingoperation for the integrator capacitor 430-b. For example, at 502 theswitching component 420-e may be deactivated, such that the voltagesource 410-h (e.g., a ground or virtual ground voltage at 0V) is coupledwith the second terminal 432-b of the integrator capacitor 430-b, andthe voltage source 410-e is coupled with the first terminal 431-b of theintegrator capacitor 430-b. Thus, the integrator capacitor 430-b may becharged according to the voltage difference between the voltage source410-e and the voltage source 410-h.

At 503, the access procedure may include activating switching component420-b (e.g., by activating logical signal SW₂). Activating switchingcomponent 420-b may initiate a precharging operation for the digit line210-a. For example, activating switching component 420-b may connect thesignal line 280-a with the digit line 210-a, which may be coupled withthe voltage source 410-a (e.g., a ground or virtual ground voltage) byway of the intrinsic capacitance 260-a. As fed by the voltage source410-d, charge may flow through the amplifier 275-a and build on thedigit line 210-a, causing the voltage on the digit line 210-a to rise.The voltage of the digit line 210-a may rise until the threshold voltageof the amplifier 275-a (e.g., threshold voltage V_(th,amp)) is no longerexceeded. Thus, after activating switching component 420-b, the voltageof the digit line 210-a may rise to a voltage level of V₁₁−V_(th,amp) ascharge flows from the signal line (e.g., as fed by the voltage source410-d, and the digit line 210-a, including intrinsic capacitance 260-a,may be charged according to the voltage difference between the voltagelevel V₁₁−V_(th,amp) and the voltage source 410-a (e.g., 0V). In someexamples, the voltage level V₁₁ may be selected such that the digit line210-a is precharged to substantially the same level as the signal line280-a. For example, the voltage level V₁₁ may be set at a level ofV₃+V_(th,amp), which may be provided by a voltage supply having avoltage level greater than voltage source 410-d. Thus, in some examplesthe digit line 210-a may rise to a voltage level equal to voltage levelV₃ in response to activating switching component 420-b at 503.

Additionally or alternatively, in some examples the digit line 210-a maybe precharged by the voltage source 410-c. For example, prior toactivating switching component 420-b, the access procedure 500 mayinclude activating switching component 420-a (e.g., by activatinglogical signal SW₁). Activating switching component 420-a may initiatean alternative precharging operation for the digit line 210-a that isnot shown in timing diagram 500. As fed by the voltage source 410-c,charge may build on the digit line 210-a, causing the voltage on thedigit line 210-a to match the voltage level V₂. In some examples thevoltage level V₂ may be substantially equal to the voltage level V₃,such that the digit line 210-a and the signal line 280-a are prechargedto the same voltage prior to activating switching component 420-b. Insome examples, precharging the digit line 210-a with the voltage source410-c may reduce power consumption and/or reduce precharge timeassociated with accessing the memory cell 105-b. Following a prechargeof the digit line 210-a by the voltage source 410-c, the accessprocedure may include activating switching component 420-b (e.g., byactivating logical signal SW₂) to connect the signal line 280-a to thedigit line 210-a.

At 504, the access procedure may include deactivating the switchingcomponent 420-c (e.g., by deactivating logical signal SW₃). Deactivatingswitching component 420-c may isolate voltage source 410-d from thesignal line 280-a, and the voltage of signal line 280-a may hold atvoltage level V₃. Upon deactivating the switching component 420-c thesignal line 280-a, and thus the first terminal 431-a of the integratorcapacitor 430-a, may be floating, and the signal line 280-a may maintaina level of charge according to the capacitance of the signal line 280-a,including the capacitance of the integrator capacitor 430-a.

At 505, the access procedure may include deactivating the switchingcomponent 420-f (e.g., by deactivating logical signal SW₆). Deactivatingswitching component 420-f may isolate voltage source 410-i from thereference line 270-a, and the voltage of reference line 270-a may holdat voltage level V₄. Upon deactivating the switching component 420-f thereference line 270-a, and thus the first terminal 431-b of theintegrator capacitor 430-b, may be floating, and the reference line270-a may maintain a level of charge according to the capacitance of thesignal line 270-a, including the capacitance of the integrator capacitor430-b.

At 506, the access procedure may include activating switching component420-d (e.g., by activating logical signal SW₄). Activating switchingcomponent 420-d may cause a transition from the voltage source 410-fbeing coupled with the second terminal 432-a of the integrator capacitor430-a to the voltage source 410-g being coupled with the second terminal432-a of the integrator capacitor 430-a. By connecting the secondterminal 432-a of the integrator capacitor 430-a to a voltage source ata higher voltage, the charge stored by the integrator capacitor 430-amay be boosted to a higher voltage, and accordingly the voltage ofsignal line 280-a, coupled with the first terminal 431-a of theintegrator capacitor 430-a, may rise to voltage level (V₃+V₆). Thus,activating switching component 420-d may initiate a boosting operationfor the integrator capacitor 430-a.

At 507, the access procedure may include activating switching component420-e (e.g., by activating logical signal SW₅). Activating switchingcomponent 420-e may cause a transition from the voltage source 410-hbeing coupled with the second terminal 432-b of the integrator capacitor430-b to the voltage source 410-i being coupled with the second terminal432-b of the integrator capacitor 430-b. By connecting the secondterminal 432-b of the integrator capacitor 430-b to a voltage source ata higher voltage, the charge stored by the integrator capacitor 430-bmay be boosted to a higher voltage, and accordingly the voltage ofreference line 270-a, coupled with the first terminal 431-b of theintegrator capacitor 430-b, may rise to voltage level (V₄+V₈). Thus,activating switching component 420-e may initiate a boosting operationfor the integrator capacitor 430-b.

At 508, the access procedure may include selecting the memory cell 105-b(e.g., by activating a word line via logical signal WL). Selecting thememory cell 105-b may cause a capacitor of the memory cell 105-b to becoupled with the digit line 210-a. Accordingly, charge may be sharedbetween the memory cell 105-b, the digit line 210-a, and the signal line280-a, which may depend on the logic state (e.g., the charge and/orpolarization) stored in the memory cell 105-b.

For example, when the memory cell 105-b stores a logic 1, the capacitorof the memory cell 105-b may store a positive charge by way of apositive polarization (e.g., a charge state 305-a as described withreference to FIG. 3). Thus, when memory cell 105-b storing a logic 1 isselected, a relatively small amount of charge may flow from the digitline 210-a to the memory cell 105-b. As charge flows from the digit line210-a to the memory cell 105-b, the voltage of the digit line 210-a maydrop, which may allow the threshold voltage of the amplifier 275-a to beexceeded. When the threshold voltage of the amplifier 275-a is exceeded,charge may flow from the signal line 280-a (e.g., from the integratorcapacitor 430-a) to the digit line 210-a across the amplifier 275-a, aswell as a relatively small amount of charge from the voltage source410-1, depending on the characteristics of the amplifier 275-a.Accordingly, charge may flow to the digit line 210-a until the voltageof the digit line 210-a returns to the voltage level equal toV₁₁−V_(th,amp). When selecting the memory cell 105-b storing a logic 1,because a relatively small amount of charge flows into the memory cell105-b, the signal line 280-a may undergo a relatively small voltage dropafter selecting the memory cell 105-b, illustrated by the voltage ofV_(sig,1).

Alternatively, when the memory cell 105-b stores a logic 0, thecapacitor of the memory cell 105-b may store a negative charge by way ofa negative polarization (e.g., charge state 310-a as described withreference to FIG. 3). Thus, when memory cell 105-b storing a logic 0 isselected, a relatively large amount of charge may flow from the digitline 210-a to the memory cell 105-b. Accordingly, the signal line 280-amay undergo a relatively larger voltage drop, illustrated by the voltageof V_(sig,0), as charge flows through the amplifier 275-a to return thedigit line to the voltage level V₁₁−V_(th,amp), such that the thresholdvoltage V_(th,amp) of the amplifier 275-a is no longer exceeded. In someexamples, selecting the memory cell 105-b storing a logic 0 may resultin a partial loss of polarization of a capacitor of the memory cell105-b. In examples where a 2Pr sensing operation is employed, selectingthe memory cell 105-b storing a logic 0 may result in a reversal ofsaturation polarization of the capacitor of the memory cell 105-b, suchthat an amount of charge associated with twice the saturationpolarization flows into the memory cell 105-b. In either case, selectinga memory cell 105-b storing a logic 0 according to the present examplemay require a subsequent refresh or rewrite operation.

At 509, the access procedure may include isolating the digit line 210-afrom the signal line 280-a by deactivating the switching component 420-b(e.g., by deactivating logical signal SW₂). Isolating the digit line210-a from the signal line 280-a may prevent additional charge frombeing shared between the digit line 210-a and the signal line 280-a,including charge sharing across the amplifier 275-a that may be causedby the threshold voltage of the amplifier 275-a being exceeded as aresult of subsequent sensing operations.

At 510, the access procedure may include deactivating switchingcomponent 420-d (e.g., by deactivating logical signal SW₄). Deactivatingswitching component 420-d may cause a transition from the voltage source410-g being coupled with the second terminal 432-a of the integratorcapacitor 430-a to the voltage source 410-f being coupled with thesecond terminal 432-a of the integrator capacitor 430-a. By connectingthe second terminal 432-a of the integrator capacitor 430-a to thevoltage source at a lower voltage, the charge stored by the integratorcapacitor 430-b may be shifted to a lower voltage, and accordingly thevoltage of signal line 280-a, coupled with the first terminal 431-a ofthe integrator capacitor 430-a, may drop by voltage level of (V₆−V₅, orjust V₆ in the event that voltage source 410-f is coupled with a commonground point). Thus, deactivating switching component 420-d may initiatea shifting operation for the integrator capacitor 430-a, which mayreduce the voltage of the signal line 280-a to a level that may be readby the sense component 130-b (e.g., a voltage between V₉ and V₁₀representing the low and high voltage sources of the sense component130-b). For example, after the shifting operation of 510, V_(sig,1) maybe approximately 1.5V as sensed by the sense component 130-b, andV_(sig,0) may be approximately 1.2V as sensed by the sense component130-b.

At 511, the access procedure may include deactivating switchingcomponent 420-e (e.g., by deactivating logical signal SW₅). Deactivatingswitching component 420-e may cause a transition from the voltage source410-i being coupled with the second terminal 432-b of the integratorcapacitor 430-b to the voltage source 410-h being coupled with thesecond terminal 432-b of the integrator capacitor 430-b. By connectingthe second terminal 432-b of the integrator capacitor 430-b to thevoltage source at a lower voltage, the charge stored by the integratorcapacitor 430-b may be shifted to a lower voltage, and accordingly thevoltage of reference line 270-a, coupled with the first terminal 431-bof the integrator capacitor 430-b, may drop by voltage level of (V₈−V₇,or just V₈ in the event that voltage source 410-h is coupled with acommon ground point). Thus, deactivating switching component 420-e mayinitiate a shifting operation for the integrator capacitor 430-b, whichmay reduce the voltage of the reference line 270-a to a level that maybe read by the sense component 130-b (e.g., a voltage between V₉ andV₁₀). For example, after the shifting operation of 511, V_(ref) may beapproximately 1.35V as sensed by the sense component 130-b.

At 512 the access procedure may include isolating the sense component130-b from the signal line 280-a by deactivating switching component420-g (e.g., by deactivating logical signal ISO₁). Isolating the sensecomponent 130-b from the signal line 280-a may allow the sense component130-b to store a voltage and/or charge associated with the signal linevoltage (e.g., V_(sig), at the first terminal 131-b of the sensecomponent 130-b) prior to determining the logic state stored in thememory cell 105-b.

At 513 the access procedure may include isolating the sense component130-b from the reference line 270-a by deactivating switching component420-h (e.g., by deactivating logical signal ISO₂). Isolating the sensecomponent 130-b from the reference line 270-a may allow the sensecomponent 130-b to store a voltage and/or charge associated with thereference line voltage (e.g., V_(ref), at the second terminal 132-b ofthe sense component 130-b) prior to determining the logic state storedin the memory cell 105-b.

At 514 the access procedure may include detecting a difference betweenthe stored voltages at the first terminal 131-b and the second terminal132-b of the sense component 130 b. For example, if the signal stored atthe first terminal 131-b is greater than the signal stored at the secondterminal 132-b (e.g., V_(sig,1)>V_(ref)), the sense component 130-b mayoutput a voltage equal to the high voltage source of the sense component(e.g., V₁₀, associated with voltage source 410-k). If the signal storedat the first terminal 131-b is less than the signal stored at the secondterminal 132-b (e.g., V_(sig,0)<V_(ref)), the sense component 130-b mayoutput a voltage equal to the low voltage source of the sense component(e.g., V₉, associated with voltage source 410-j).

Although illustrated as separate operations occurring at differenttimes, certain operations may occur simultaneously, or in a differentorder. In some examples, various operations may be advantageouslyinitiated simultaneously in order to reduce the amount of time requiredto sense a logic state of the memory cell 105-b. For example, theinitiation of precharging at 501 and 502 may occur in an opposite order,or simultaneously (e.g., when logical signals SW₃ and SW₆ are driven asa common logical signal). Further, connecting the digit line 210-a withthe signal line 280-a at 503 may occur prior to 501 and/or 502, or allthree operations may occur simultaneously. Boosting the signal line280-a at 506 and boosting the reference line 270-a at 507 may also occurin an opposite order, or simultaneously (e.g., when using a commonvariable voltage source 450, or when logical signals SW₄ and SW₅ aredriven as a common logical signal). Similarly, shifting the signal line280-a at 510 and shifting the reference line 270-a at 511 may also occurin an opposite order or simultaneously. In some examples, isolating thesense component 130-b from the signal line 280-a at 512 and isolatingthe sense component 130-b from the reference line 270-a at 513 may occurin an opposite order, or simultaneously (e.g., when logical signals ISO₁and ISO₂ are driven as a common logical signal).

In some examples, boosting and shifting of the reference line 270-a maybe eliminated altogether, and thus operations at 508 and 511 may beomitted. Thus, in some embodiments, the second integrator capacitor430-b and the second variable voltage source 450-b may be omitted fromthe circuit 400, and self-boost may still be supported for signalgeneration when accessing the memory cell 105-b.

The order of operations shown in timing diagram 500 is for illustrationonly, and various other orders and combinations of steps may beperformed to support self-boost in accordance with the presentdisclosure. Further, the timing of the operations of timing diagram 500is also for illustration purposes only, and is not meant to indicate aparticular relative duration between one operation and another. Variousoperations may occur over a duration that is relatively shorter orrelatively longer than illustrated in various embodiments of self-boostin accordance with the present disclosure.

The transitions of the logical signals of the timing diagram 500 areillustrative of transitions from one state to another, and generallyreflect transitions between an enabled or activated state (e.g., state“0”) and a disabled or deactivated state (e.g., state “1”) as associatedwith a particular numbered operation. In various examples the states maybe associated with a particular voltage of the logical signal (e.g., alogical input voltage applied to a gate of a transistor operating as aswitch), and the change in voltage from one state to another may not beinstantaneous. Rather, in some examples a voltage associated with alogical signal may follow a curve over time from one logical state toanother. Thus, the transitions shown in timing diagram 500 are notnecessarily indicative of an instantaneous transition. Further, theinitial state of a logical signal associated with a transition at anumbered operation may have been arrived during various times precedingthe numbered operation while still supporting the described transitionsand associated operations.

FIG. 6 illustrates an example of a circuit 600 that may supportself-boost, source following, and sense-and-hold for accessing memorycells in accordance with various embodiments of the present disclosure.The circuit 600 includes a sense component 130-c for sensing a logicstate of a memory cell 105-c. Electrical signals may be communicatedbetween the sense component 130-c and the memory cell 105-c via a digitline 210-b, a signal line 280-b, and a source follower signal line 602,which may, in combination, be referred to as a single access line of thememory cell 105-b. Signals of the access line may be illustrated byvoltage V_(DL) on the digit line 210-b, V_(sig) on the signal line280-b, and V_(SF) on the source follower signal line 602, as shown. Theexample circuit 600 may include an amplifier 275-b coupled between thedigit line 210-b and the signal line 280-b, which may be enabled byvoltage source 610-n. The example circuit 600 may also include a sourcefollower amplifier 640-a coupled between the signal line 280-a and thesource follower signal line 602, and a source follower load component645-a coupled between the source follower signal line 602 and a voltagesource 610-k having a voltage V₁₁, which may be enabled or disabled by asignal EQA. Thus, the memory cell 105-c may represent a memory cellcoupled between a first access line (e.g., the digit line 210-b, thesignal line 280-a, and the source follower signal line 602) and a secondaccess line (e.g., the word line 205-b).

The circuit 600 may also include a reference line 270-b and a sourcefollower reference line 604. A source follower amplifier 640-b may becoupled between the reference line 270-b and the source followerreference line 604, and a source follower load component 645-b coupledbetween the source follower reference line 604 and a voltage source610-m having a voltage V₁₂, which may be enabled or disabled by a signalEQB. The source follower reference line 604 may provide a referencesignal for comparison with a signal of the source follower signal line602 when detecting a logic state of the memory cell 105-c. The circuit600 may also include a word line 205-b for selecting or deselecting thememory cell 105-c (e.g., by way of logic signal WL), and a plate line215-b for accessing a cell plate of a capacitor of the memory cell105-c. In some examples the circuit 600 may also include a write line660, which may support various write operations, and may provide aconnection or isolation between the sense component 130-c and the digitline 210-b by enabling or disabling a switching component 620-k (e.g.,by activating or deactivating logical signal ISOW).

The circuit 600 may include a variety of voltage sources 610, which maybe coupled with various voltage supplies and/or common grounding orvirtual grounding points of a memory device that includes the examplecircuit 600.

A voltage source 610-a may represent a common grounding point (e.g., achassis ground, a neutral point, etc.), which may provide a commonreference voltage having a voltage V₀, from which other voltages aredefined. The voltage source 610-a may be coupled with the digit line210-b via the intrinsic capacitance 260-b of the digit line 210-b.

A voltage source 610-b having a voltage V₁ may represent a plate linevoltage source, and may be coupled with the memory cell 105-c via aplate line 215-b of the memory cell 105-c.

A voltage source 610-c having a voltage V₂ may represent a digit linevoltage source, and may be coupled with the digit line 210-b via aswitching component 620-a, which may be activated or deactivated by alogical signal SW₁.

A voltage source 610-d having a voltage V₃ may represent a signal lineprecharge voltage source, and may be coupled with the signal line 280-bvia a switching component 620-c, which may be activated or deactivatedby a logical signal SW₃.

A voltage source 610-e having a voltage V₄ may represent a referencesignal voltage source, and may be coupled with the reference line 270-bvia a switching component 620-f, which may be activated or deactivatedby a logical signal SW₆.

A voltage source 610-n having a voltage V₁₃ may represent a digit linevoltage source, and may be coupled with an amplifier 275-b which may bean example of the amplifier 275 or 275-a described with reference toFIGS. 2 and 4. For example, the amplifier 275-b may be a transistor, andthe voltage source 610-n may be coupled with the gate of the transistor.The amplifier 275-b may be coupled with the signal line 280-b at a firstterminal, and the digit line 210-b at a second terminal. The amplifier275-b may provide a conversion of signals between the digit line 210-band the signal line 280-b. For example, the amplifier 275-b may permit aflow of charge (e.g., electrical current) from the signal line 280-b tothe digit line 210-b, as fed or enabled by the voltage source 610-n,upon a reduction in voltage of the digit line 210-b (e.g., uponselection of the memory cell 105-c). A relatively small flow of chargeto the digit line 210-b may be associated with a relatively small changein voltage of the signal line 280-b, whereas a relatively large flow ofcharge to the digit line 210-b may be associated with a relatively largechange in voltage of the signal line 280-b. According to the netcapacitance of the signal line 280-b, for example, the signal line 280-bmay undergo a relatively small change in voltage or a relatively largechange in voltage depending on the flow of charge across the amplifier275-b after selecting the memory cell 105-b. In some examples theamplifier 275-b may be isolated from the digit line 210-b by a switchingcomponent 620-b, which may be activated or deactivated by a logicalsignal SW₂. The amplifier 275-b may also referred to as a “voltageregulator” or a “bias component,” relating to how the amplifier 275-bregulates a flow of charge in response to the voltage of the digit line210-b.

The circuit may also include a first integrator capacitor 630-b and asecond integrator capacitor 630-b, which may each be coupled with arespective variable voltage source 650. Integrator capacitors 630 may beexamples of the integrator capacitors 430 described with reference toFIG. 4, and variable voltage sources 650 may be examples of the variablevoltage sources 450 described with reference to FIG. 4. For example, thefirst integrator capacitor 630-a may be coupled with the signal line280-b at a first terminal 631-a, and coupled with a variable voltagesource 650-a at a second terminal 632-a. The second integrator capacitor630-b may be coupled with the reference line 270-b at a first terminal631-b, and coupled with a variable voltage source 650-b at a secondterminal 632-b

In the example of circuit 600, the variable voltage source 650-a mayinclude a voltage source 610-f having a voltage V₅ and a voltage source610-g having a voltage V₆, which may be selected for connection with thefirst integrator capacitor 630-a by a switching component 620-d by wayof a logical signal SW₄. In some examples the voltage source 610-f maybe coupled with a common grounding point (not shown). In other examplesthe voltage source 610-f may be coupled with a voltage supply thatprovides a positive or negative voltage. Voltage source 610-g may becoupled with a voltage supply having a higher voltage than that ofvoltage source 610-f, thereby providing the boosting functions asdescribed herein (e.g., in accordance with the difference in voltagebetween voltage source 610-g and 610-f, equal to V₆−V₅, or simply V₆when the voltage source 610-f is grounded).

In the example of circuit 600, the variable voltage source 650-b mayinclude a voltage source 610-h having a voltage V₇ and a voltage source610-i having a voltage V₈, which may be selected for connection with thesecond integrator capacitor 630-b by a switching component 620-e by wayof a logical signal SW₅. In some examples the voltage source 610-h maybe coupled with a common grounding point (not shown). In other examplesthe voltage source 610-h may be coupled with a voltage supply thatprovides a positive or negative voltage. Voltage source 610-i may becoupled with a voltage supply having a higher voltage than that ofvoltage source 610-h, thereby providing the boosting functions asdescribed herein (e.g., in accordance with the difference in voltagebetween voltage source 610-i and 610-h, equal to V₈−V₇, or simply V₈when the voltage source 610-h is grounded).

Although circuit 600 is shown as including two variable voltage sources650, some configurations in accordance with the present disclosure mayinclude a single, common variable voltage source 650. In some examplesthat use a common variable voltage source 650, the source voltageprovided to the second terminal 632-a of the first integrator capacitor630-a may be different to the source voltage provided to the secondterminal 632-b of the second integrator capacitor 630-b due todifferences in the circuit (e.g., conductor length, width, resistance,capacitance, etc.) between the variable voltage source 650 and each ofthe integrator capacitors 630. Further, although a variable voltagesource 650 is illustrated as including two voltage sources 610 and aswitching component 620, a variable voltage source 650 supporting theoperations herein may include other configurations, such as a voltagebuffer that provides a variable voltage to one or both of the secondterminal 632-a of the first integrator capacitor 630-a and the secondterminal 632-b of the second integrator capacitor 630-b.

Source follower amplifiers 640-a and 640-b may be configured to supportsource following in accordance with embodiments of the presentdisclosure. For example, source follower amplifier 640-a may be atransistor, and the signal line 280-b may be coupled with a gateterminal of the transistor. The source follower amplifier 640-a may befed by a voltage source 610-j having a voltage V₉, which may represent asignal source follower voltage source. The voltage source 610-j may becoupled with the source follower amplifier 640-a via a switchingcomponent 620-i, which may be activated or deactivated by a logicalsignal SW₇. Thus, logical signal SW₇ may be used to enable or disablethe source follower amplifier 640-a for generating the signal sourcefollower voltage V_(sig,SF) on the source follower signal line 602,where V_(sig,SF) may be equal to V_(sig) minus the threshold voltage,V_(th,1), of the transistor of the source follower amplifier 640-a.

Similarly, source follower amplifier 640-b may also be a transistor, andthe reference line 270-b may be coupled with a gate terminal of thetransistor. The source follower amplifier 640-b may be fed by a voltagesource 610-1 having a voltage V₁₁, which may represent a referencesource follower voltage source. The voltage source 610-1 may be coupledwith the source follower amplifier 640-b via a switching component620-j, which may be activated or deactivated by a logical signal SW₈.Thus, logical signal SW₈ may be used to enable or disable the sourcefollower amplifier 640-b for generating the reference source followervoltage V_(ref,SF) on the source follower reference line 604, whereV_(ref,SF) may be equal to V_(ref) minus the threshold voltage V_(th,2)of the transistor of the source follower amplifier 640-b.

To support various operations described herein, the sense component130-c may be isolated from portions of the circuit 600. For example, thesense component 130-c may be coupled with the source follower signalline 602 via a switching component 620-g (e.g., an isolation component),which may be activated or deactivated by a logical signal ISO₁.Additionally or alternatively, the sense component 130-c may be coupledwith the source follower reference line 604 via a switching component620-h (e.g., an isolation component), which may be activated ordeactivated by a logical signal ISO₂. Further, the sense component 130-cmay be coupled with a low voltage source and a high voltage source (notshown), which may be examples of sense component voltage sources 256-band 265-c described with reference to FIG. 2, respectfully.

Each of the logical signals illustrated in circuit 600 may be providedby a memory controller (not shown), such as a memory controller 150described with reference to FIG. 1. In some examples, certain logicalsignals may be provided by other components. For example, logical signalWL may be provided by a row decoder (not shown), such as a row decoder125 described with reference to FIG. 1.

In various examples, voltage sources 610 may be coupled with differentconfigurations of voltage supplies and/or common grounding or virtualgrounding points of a memory device that includes the example circuit600. For example, in some embodiments voltage sources 610-a, 610-f,610-h, 610-k, and 610-m, or any combination thereof, may be coupled withthe same ground point or virtual ground point, and may providesubstantially the same reference voltage for various operations ofaccessing the memory cell 105-c. In some embodiments, several voltagesources 610 may be coupled with the same voltage supply of a memorydevice. For example, in some embodiments, voltage sources 610-c, 610-d,610-g, 610-i. 610-j, and 610-l, or any combination thereof, may becoupled with a voltage supply having a certain voltage (e.g., a voltageof 1.5V, which may be referred to as “VARY”). In such embodiments, thesignal line 280-b may be boosted to a voltage substantially equal to2*VARY, or approximately 3.0V, prior to selecting the memory cell 105-cvia word line 205-b for sensing. Thus, in accordance with embodiments ofthe present disclosure, self-boost operations may overcome a need toprovide a relatively higher voltage supply for sense operations (e.g., avoltage source of 3.0V or more, which in some applications may refer toa “positive pump” voltage of V_(pp)). In other examples, voltage sources610-g and 610-i may be coupled with a different voltage supply thanother voltage supplies (e.g., a voltage of 1.2V, which may be referredto as “PDS”), which may thus be associated with a voltage boost of 1.2V.Although voltage sources 610 may be coupled with common voltage suppliesand/or grounding points, the voltage of each of the voltage sources 610coupled with a common voltage supply or common grounding point may bedifferent due to differences in the circuit (e.g., conductor length,width, resistance, capacitance, etc.) between the respective voltagesources 610 and the associated common voltage supply or common groundingpoint.

Voltage source 610-e may provide a reference voltage for sensing thelogic state of the memory cell 105-c, such that V₄ is an average voltagebetween signal voltage associated with sensing a logic 1 and a logic 0.In some examples, a voltage of V₄ may be provided as a voltage droppedfrom a voltage supply of the memory device, which may be the samevoltage supply coupled with other voltage sources 610. For example, V₄may be provided by connecting voltage source 610-e with a same voltagesupply as voltage source 610-d, but with an intervening electrical load(e.g., a resistive load or capacitance) between the voltage supply andthe voltage source 610-e.

FIG. 7 shows a timing diagram 700 illustrating operations of an exampleaccess procedure that may support self-boost and source following foraccessing memory cells in accordance with various embodiments of thepresent disclosure. The example access procedure is described withreference to components of the example circuit 600 described withreference to FIG. 6.

In the example of timing diagram 700, voltage sources 610-a, 610-f,610-h, 610-k, and 610-m are considered to be grounded, and therefore ata zero voltage (e.g., V₀=0V, V₅=0V, V₇=0V, V₁₀=0V, and V₁₂=0V). However,in other examples voltage sources 610-a, 610-f, 610-h, 610-k, and 610-mmay be at non-zero voltages, and the voltages of timing diagram 700 maythus be adjusted accordingly. In some examples, prior to initiating theoperations of timing diagram 700, the digit line 210-b and the plateline 215-b may be controlled to the same voltage, which may minimizecharge leakage across the memory cell 105-c. For example, according tothe timing diagram 700, the digit line 210-b has an initial voltage of0V, which may be the same as the initial voltage of the plate line215-b. In other examples, the digit line 210-b and the plate line 215-bmay have some other initial voltage different from the ground voltage.

At 701, the access procedure may include activating switching component620-c (e.g., by activating logical signal SW₃). Activating switchingcomponent 620-c may connect voltage source 610-d with the signal line280-b, and accordingly the voltage of signal line 280-b may rise tovoltage level V₃ as charge flows into the integrator capacitor 630-a.Thus, activating switching component 620-c may initiate a prechargingoperation for the integrator capacitor 630-a. For example, at 701 theswitching component 620-d may be deactivated, such that the voltagesource 610-f (e.g., a ground or virtual ground voltage at 0V) is coupledwith the second terminal 632-a of the integrator capacitor 630-a, andthe voltage source 610-d is coupled with the first terminal 631-a of theintegrator capacitor 630-a. Thus, the integrator capacitor 630-a may becharged according to the voltage difference between the voltage source610-d and the voltage source 610-f.

At 702, the access procedure may include activating switching component620-f (e.g., by activating logical signal SW₆). Activating switchingcomponent 620-f may connect voltage source 610-e with the reference line270-b, and accordingly the voltage of reference line 270-b may rise tovoltage level V₄ as charge flows into the integrator capacitor 630-b.Thus, activating switching component 620-f may initiate a prechargingoperation for the integrator capacitor 630-b. For example, at 702 theswitching component 620-e may be deactivated, such that the voltagesource 610-h (e.g., a ground or virtual ground voltage at 0V) is coupledwith the second terminal 632-b of the integrator capacitor 630-b, andthe voltage source 610-e is coupled with the first terminal 631-b of theintegrator capacitor 630-b. Thus, the integrator capacitor 630-b may becharged according to the voltage difference between the voltage source610-e and the voltage source 610-h.

At 703, the access procedure may include activating switching component620-b (e.g., by activating logical signal SW₂). Activating switchingcomponent 620-b may initiate a precharging operation for the digit line210-b. For example, activating switching component 620-b may connect thesignal line 280-b with the digit line 210-b, which may be coupled withthe voltage source 610-a (e.g., a ground or virtual ground voltage) byway of the intrinsic capacitance 260-b. As fed by the voltage source610-d, charge may flow through the amplifier 275-b and build on thedigit line 210-b, causing the voltage on the digit line 210-b to rise.The voltage of the digit line 210-b may rise until the threshold voltageof the amplifier 275-b (e.g., threshold voltage V_(th,amp)) is no longerexceeded. Thus, after activating switching component 620-b, the voltageof the digit line 210-b may rise to a voltage level of V₁₃−V_(th,amp) ascharge flows from the signal line (e.g., as fed by the voltage source610-d), and the digit line 210-b, including intrinsic capacitance 260-b,may be charged according to the voltage difference between the voltagelevel V₁₃−V_(th,amp) and the voltage source 610-a (e.g., 0V). In someexamples, the voltage level V₁₃ may be selected such that the digit line210-b is precharged to substantially the same level as the signal line280-b. For example, the voltage level V₁₃ may be set at a level ofV₃+V_(th,amp), which may be provided by a voltage supply having avoltage level greater than voltage source 610-d. Thus, in some examplesthe digit line 210-b may rise to a voltage level equal to voltage levelV₃ in response to activating switching component 620-b at 703.

Additionally or alternatively, in some examples the digit line 210-b maybe precharged by the voltage source 610-c. For example, prior toactivating switching component 620-b, the access procedure 700 mayinclude activating switching component 620-a (e.g., by activatinglogical signal SW₁). Activating switching component 620-a may initiatean alternative precharging operation for the digit line 210-b that isnot shown in timing diagram 700. As fed by the voltage source 610-c,charge may build on the digit line 210-b, causing the voltage on thedigit line 210-b to match the voltage level V₂. In some examples thevoltage level V₂ may be substantially equal to the voltage level V₃,such that the digit line 210-b and the signal line 280-b are prechargedto the same voltage prior to activating switching component 620-b. Insome examples, precharging the digit line 210-b with the voltage source610-c may reduce power consumption and/or reduce precharge timeassociated with accessing the memory cell 105-c. Following a prechargeof the digit line 210-b by the voltage source 610-c, the accessprocedure may include activating switching component 620-b (e.g., byactivating logical signal SW₂) to connect the signal line 280-b to thedigit line 210-b.

At 704, the access procedure may include deactivating the switchingcomponent 620-c (e.g., by deactivating logical signal SW₃). Deactivatingswitching component 620-c may isolate voltage source 610-d from thesignal line 280-b, and the voltage of signal line 280-b may hold atvoltage level V₃. Upon deactivating the switching component 620-c thesignal line 280-b, and thus the first terminal 631-a of the integratorcapacitor 630-a, may be floating, and the signal line 280-b may maintaina level of charge according to the capacitance of the signal line 280-b,including the capacitance of the integrator capacitor 630-a.

At 705, the access procedure may include deactivating the switchingcomponent 620-f (e.g., by deactivating logical signal SW₆). Deactivatingswitching component 620-f may isolate voltage source 610-i from thereference line 270-b, and the voltage of reference line 270-b may holdat voltage level V₄. Upon deactivating the switching component 620-f thereference line 270-b, and thus the first terminal 631-b of theintegrator capacitor 630-b, may be floating, and the reference line270-b may maintain a level of charge according to the capacitance of thesignal line 270-b, including the capacitance of the integrator capacitor630-b.

At 706, the access procedure may include activating switching component620-d (e.g., by activating logical signal SW₄). Activating switchingcomponent 620-d may cause a transition from the voltage source 610-fbeing coupled with the second terminal 632-a of the integrator capacitor630-a to the voltage source 610-g being coupled with the second terminal632-a of the integrator capacitor 630-a. By connecting the secondterminal 632-a of the integrator capacitor 630-a to a voltage source ata higher voltage, the charge stored by the integrator capacitor 630-amay be boosted to a higher voltage, and accordingly the voltage ofsignal line 280-b, coupled with the first terminal 631-a of theintegrator capacitor 630-a, may rise to voltage level (V₃+V₆). Thus,activating switching component 620-d may initiate a boosting operationfor the integrator capacitor 630-a.

At 707, the access procedure may include activating switching component620-e (e.g., by activating logical signal SW₅). Activating switchingcomponent 620-e may cause a transition from the voltage source 610-hbeing coupled with the second terminal 632-b of the integrator capacitor630-b to the voltage source 610-i being coupled with the second terminal632-b of the integrator capacitor 630-b. By connecting the secondterminal 632-b of the integrator capacitor 630-b to a voltage source ata higher voltage, the charge stored by the integrator capacitor 630-bmay be boosted to a higher voltage, and accordingly the voltage ofreference line 270-b, coupled with the first terminal 631-b of theintegrator capacitor 630-b, may rise to voltage level (V₄+V₈). Thus,activating switching component 620-e may initiate a boosting operationfor the integrator capacitor 630-b.

At 708, the access procedure may include selecting the memory cell 105-c(e.g., by activating a word line via logical signal WL). Selecting thememory cell 105-c may cause a capacitor of the memory cell 105-c to becoupled with the digit line 210-b. Accordingly, charge may be sharedbetween the memory cell 105-c, the digit line 210-b, and the signal line280-b, which may depend on the logic state (e.g., the charge and/orpolarization) stored in the memory cell 105-c.

For example, when the memory cell 105-c stores a logic 1, the capacitorof the memory cell 105-c may store a positive charge by way of apositive polarization (e.g., a charge state 305-a as described withreference to FIG. 3). Thus, when memory cell 105-c storing a logic 1 isselected, a relatively small amount of charge may flow from the digitline 210-b to the memory cell 105-c. As charge flows from the digit line210-b to the memory cell 105-c, the voltage of the digit line 210-b maydrop, which may allow the threshold voltage of the amplifier 275-b to beexceeded. When the threshold voltage of the amplifier 275-b is exceeded,charge may flow from the signal line 280-b (e.g., from the integratorcapacitor 630-a) to the digit line 210-b across the amplifier 275-b, aswell as a relatively small amount of charge from the voltage source610-n, depending on the characteristics of the amplifier 275-b.Accordingly, charge may flow to the digit line 210-b until the voltageof the digit line 210-b returns to the voltage level equal toV₁₃−V_(th,amp). When selecting the memory cell 105-c storing a logic 1,because a relatively small amount of charge flows into the memory cell105-c, the signal line 280-b may undergo a relatively small voltage dropafter selecting the memory cell 105-c, illustrated by the voltage ofV_(sig,1).

Alternatively, when the memory cell 105-c stores a logic 0, thecapacitor of the memory cell 105-c may store a negative charge by way ofa negative polarization (e.g., charge state 310-a as described withreference to FIG. 3). Thus, when memory cell 105-c storing a logic 0 isselected, a relatively large amount of charge may flow from the digitline 210-b to the memory cell 105-c. Accordingly, the signal line 280-bmay undergo a relatively larger voltage drop, illustrated by the voltageof V_(sig,0), as charge flows through the amplifier 275-b to return thedigit line to the voltage level V₁₃−V_(th,amp), such that the thresholdvoltage V_(th,amp) of the amplifier 275-b is no longer exceeded. In someexamples, selecting the memory cell 105-c storing a logic 0 may resultin a partial loss of polarization of a capacitor of the memory cell105-c. In examples where a 2Pr sensing operation is employed, selectingthe memory cell 105-c storing a logic 0 may result in a reversal ofsaturation polarization of the capacitor of the memory cell 105-c, suchthat an amount of charge associated with twice the saturationpolarization flows into the memory cell 105-c. In either case, selectinga memory cell 105-c storing a logic 0 according to the present examplemay require a subsequent refresh or rewrite operation.

At 709, the access procedure may include isolating the digit line 210-bfrom the signal line 280-b by deactivating the switching component 620-b(e.g., by deactivating logical signal SW₂). Isolating the digit line210-b from the signal line 280-b may prevent additional charge frombeing shared between the digit line 210-b and the signal line 280-b,including charge sharing across the amplifier 275-b that may be causedby the threshold voltage of the amplifier 275-b being exceeded as aresult of subsequent sensing operations.

At 710, the access procedure may include deactivating switchingcomponent 620-d (e.g., by deactivating logical signal SW₄). Deactivatingswitching component 620-d may cause a transition from the voltage source610-g being coupled with the second terminal 632-a of the integratorcapacitor 630-a to the voltage source 610-f being coupled with thesecond terminal 632-a of the integrator capacitor 630-a. By connectingthe second terminal 632-a of the integrator capacitor 630-a to thevoltage source at a lower voltage, the charge stored by the integratorcapacitor 630-b may be shifted to a lower voltage, and accordingly thevoltage of signal line 280-b, coupled with the first terminal 631-a ofthe integrator capacitor 630-a, may drop by voltage level of (V₆−V₅, orjust V₆ in the event that voltage source 610-f is coupled with a commonground point). Thus, deactivating switching component 620-d may initiatea shifting operation for the integrator capacitor 630-a, which mayreduce the voltage of the signal line 280-b to a level that may be readby the sense component 130-c (e.g., a voltage between low and highvoltage sources of the sense component 130-c, not shown). For example,after the shifting operation of 710, V_(sig,1) may be approximately1.5V, and V_(sig,0) may be approximately 1.2V.

At 711, the access procedure may include deactivating switchingcomponent 620-e (e.g., by deactivating logical signal SW₅). Deactivatingswitching component 620-e may cause a transition from the voltage source610-i being coupled with the second terminal 632-b of the integratorcapacitor 630-b to the voltage source 610-h being coupled with thesecond terminal 632-b of the integrator capacitor 630-b. By connectingthe second terminal 632-b of the integrator capacitor 630-b to thevoltage source at a lower voltage, the charge stored by the integratorcapacitor 630-b may be shifted to a lower voltage, and accordingly thevoltage of reference line 270-b, coupled with the first terminal 631-bof the integrator capacitor 630-b, may drop by voltage level of (V₈−V₇,or just V₈ in the event that voltage source 610-h is coupled with acommon ground point). Thus, deactivating switching component 620-e mayinitiate a shifting operation for the integrator capacitor 630-b, whichmay reduce the voltage of the reference line 270-b to a level that maybe read by the sense component 130-c (e.g., a voltage between low andhigh voltage sources of the sense component 130-c, not shown). Forexample, after the shifting operation of 711, V_(ref) may beapproximately 1.35V.

At 712, the access procedure may include enabling the source followeramplifier 640-a coupled between the signal line 280-b and the sourcefollower signal line 602. For example, the source follower amplifier640-a may be a transistor, and enabling the source follower amplifier640-a may include connecting a source of the transistor with voltagesource 610-j, having a voltage V₉, by enabling the switching component620-i (e.g., by activating logical signal SW₇). Connecting the sourcefollower amplifier 640-a with the voltage source 610-j may supportcharge flowing through the source follower amplifier 640-a from thesignal line 280-b to the source follower signal line 602, and also anamplified charge (e.g., a multiple of the charge flowing from the signalline 280-b) flowing through the source follower amplifier 640-a from thevoltage source 610-j to the source follower signal line 602.Accordingly, charge may accumulate on the source follower signal line602 until the voltage threshold of the transistor is no longer exceeded.In other words, the voltage of the source follower signal line 602 mayrise to a level of V_(sig,SF)=(V_(sig)−V_(th,1)), where V₁₁ is thethreshold voltage of the transistor of the source follower amplifier640-a. For example, V₁₁ may be approximately 0.5V, so that afterenabling the source follower amplifier 640-a, V_(sig,SF,1) may beapproximately 1.0V, and V_(sig,SF,0) may be approximately 0.7V.

In some examples the voltage of the signal line 280-b may only drop by anegligible amount upon enabling the source follower amplifier 640-a,because only a trivial amount of charge flows from the signal line 280-bto the source follower signal line 602. Although the voltage of thesource follower signal line 602 may be lower than the voltage of thesignal line 280-b, the increased amount of charge provided to the sourcefollower signal line 602 may support larger components in the sensecomponent 130-c, and may also limit charge sharing between the signalline 280-b and the sense component 130-c. Limiting charge sharingbetween the signal line 280-b and the sense component 130-c may improveself-boost operations (e.g., by reducing the effective access linecapacitance that may otherwise be present without such source followingembodiments), and may improve signal development upon accessing thememory cell 105-c. Thus, various embodiments of source following may beemployed to improve the robustness of logic state detection.

In some examples, the source follower load component 645-a may also beenabled during the operations of 712. In examples where the sourcefollower load component 645-a is a transistor, signal EQA may be enabledat the gate of the transistor, which may support current flowing throughthe source follower amplifier 640-a to also flow through the sourcefollower load component 645-a. Thus, in some examples the sourcefollower load component 645-a may operate as a current generator tosupport source following functionality. Although signal EQA may besubstantially a digital signal having a relatively high voltage suchthat a transistor of the source follower load component 645-a operatesin a saturation region, signal EQA may also be selected such that atransistor of the source follower load component 645-a operates in alinear, or ohmic region. In other words, signal EQA may be selected inorder to operate the source follower load component 645-a at aparticular working point. Further, although signal EQA may be enabledduring source follower operations of 712, signal EQA may be disabled atother times (e.g., prior to 712, or after developing V_(sig,SF)), whichmay reduce energy consumption.

At 713, the access procedure may include enabling the source followeramplifier 640-b coupled between the reference line 270-b and the sourcefollower reference line 604. For example, the source follower amplifier640-b may also be a transistor, and enabling the source followeramplifier 640-b may include connecting a source of the transistor withvoltage source 610-1, having a voltage V₁₁, by enabling the switchingcomponent 620-j (e.g., by activating logical signal SW₈). Connecting thesource follower amplifier 640-b with the voltage source 610-1 maysupport charge flowing through the source follower amplifier 640-b fromthe reference line 270-b to the source follower reference line 604, andalso an amplified charge (e.g., a multiple of the charge flowing fromthe reference line 270-b) flowing through the source follower amplifier640-b from the voltage source 610-1 to the source follower referenceline 604. Accordingly, charge may accumulate on the source followerreference line 604 until the voltage threshold of the transistor is nolonger exceeded. In other words, the voltage of the source followerreference line 604 may rise to a level of V_(ref,SF)=(V_(ref)−N_(th,2)),where V_(th,ref) is the threshold voltage of the transistor of thesource follower amplifier 640-b. For example, V_(th,2) may also beapproximately 0.5V, so that after enabling the source follower amplifier640-g, V_(ref,SF) may be approximately 0.85V.

In some examples the voltage of the reference line 270-b may only dropby a negligible amount upon enabling the source follower amplifier640-b, because only a trivial amount of charge flows from the referenceline 270-b to the source follower reference line 604. Although thevoltage of the source follower reference line 604 may be lower than thevoltage of the reference line 270-b, the increased amount of chargeprovided to the source follower reference line 604 may support largercomponents in the sense component 130-c, and may also limit chargesharing between the reference line 270-b and the sense component 130-c.

In some examples, the source follower load component 645-b may also beenabled during the operations of 713. In examples where the sourcefollower load component 645-b is a transistor, signal EQB may be enabledat the gate of the transistor, which may support current flowing throughthe source follower amplifier 640-b to also flow through the sourcefollower load component 645-b. Thus, in some examples the sourcefollower load component 645-b may operate as a current generator tosupport source following functionality. Although signal EQB may besubstantially a digital signal having a relatively high voltage suchthat a transistor of the source follower load component 645-b operatesin a saturation region, signal EQB may also be selected such that atransistor of the source follower load component 645-b operates in alinear, or ohmic region. In other words, signal EQB may be selected inorder to operate the source follower load component 645-b at aparticular working point. Further, although signal EQB may be enabledduring source follower operations of 713, signal EQB may be disabled atother times (e.g., prior to 713, or after developing V_(ref,SF)), whichmay reduce energy consumption. In various examples, signals EQA and EQBmay be provided by the same, or different controller outputs or voltagesupplies. For example, signals EQA and EQB may be selected to have thesame voltage, which may support source follower load component 645-a andsource follower load component 645-b operating at substantially the sameworking point. Further, signals EQA and EQB may be enabled or disabledat the same times, or different times, according to differentembodiments.

At 714, the access procedure may include isolating the sense component130-c from the source follower signal line 602 by deactivating switchingcomponent 620-g (e.g., by deactivating logical signal ISO₁). Isolatingthe sense component 130-c from the source follower signal line 602 mayallow the sense component 130-c to store a voltage and/or chargeassociated with the source follower signal line voltage at a firstterminal of the sense component 130-c prior to determining the logicstate stored in the memory cell 105-c.

At 715, the access procedure may include isolating the sense component130-c from the source follower reference line 604 by deactivatingswitching component 620-h (e.g., by deactivating logical signal ISO₂).Isolating the sense component 130-c from the source follower referenceline 604 may allow the sense component 130-c to store a voltage and/orcharge associated with the source follower reference line voltage at asecond terminal of the sense component 130-c prior to determining thelogic state stored in the memory cell 105-c.

At 716, the access procedure may include detecting a difference betweenthe stored voltages at the first and second terminals of the sensecomponent 130-c. For example, if the signal stored at the first terminalis greater than the signal stored at the second terminal (e.g.,V_(sig,SF,1)>V_(ref,SF)), the sense component 130-c may output a voltageequal to the high voltage source of the sense component. If the signalstored at the first terminal is less than the signal stored at thesecond terminal (e.g., V_(sig,SF,0)<V_(ref,SF)), the sense component130-c may output a voltage equal to the low voltage source of the sensecomponent.

Although illustrated as separate operations occurring at differenttimes, certain operations may occur simultaneously, or in a differentorder. In some examples, various operations may be advantageouslyinitiated simultaneously in order to reduce the amount of time requiredto sense a logic state of the memory cell 105-c. For example, theinitiation of precharging at 701 and 702 may occur in an opposite order,or simultaneously (e.g., when logical signals SW₃ and SW₆ are driven asa common logical signal). Further, connecting the digit line 210-b withthe signal line 280-b at 703 may occur prior to 701 and/or 702, or allthree operations may occur simultaneously. Boosting the signal line280-b at 706 and boosting the reference line 270-b at 707 may also occurin an opposite order, or simultaneously (e.g., when using a commonvariable voltage source 450, or when logical signals SW₄ and SW₅ aredriven as a common logical signal). Similarly, shifting the signal line280-b at 710 and shifting the reference line 270-b at 711 may also occurin an opposite order or simultaneously. Likewise, enabling the sourcefollower amplifier 640-a at 712 and enabling the source followeramplifier 640-b at 713 may also occur in an opposite order, orsimultaneously (e.g., when using a common voltage source 610, or whenlogical signals SW₇ and SW₈ are driven as a common logical signal). Insome examples, isolating the sense component 130-c from the signal line280-b at 712 and isolating the sense component 130-c from the referenceline 270-b at 713 may occur in an opposite order, or simultaneously(e.g., when logical signals ISO₁ and ISO₂ are driven as a common logicalsignal).

In some examples, boosting and shifting of the reference line 270-b maybe eliminated altogether, and thus operations at 707 and 711 may beomitted. Thus, in some embodiments, the second integrator capacitor630-b and the second variable voltage source 650-b may be omitted fromthe circuit 600, and self-boost and source following may still besupported for signal generation when accessing the memory cell 105-c.

The order of operations shown in timing diagram 700 is for illustrationonly, and various other orders and combinations of steps may beperformed to support self-boost in accordance with the presentdisclosure. Further, the timing of the operations of timing diagram 700is also for illustration purposes only, and is not meant to indicate aparticular relative duration between one operation and another. Variousoperations may occur over a duration that is relatively shorter orrelatively longer than illustrated in various embodiments of self-boostin accordance with the present disclosure.

The transitions of the logical signals of the timing diagram 700 areillustrative of transitions from one state to another, and generallyreflect transitions between an enabled or activated state (e.g., state“1”) and a disabled or deactivated state (e.g., state “0”) as associatedwith a particular numbered operation. In various examples the states maybe associated with a particular voltage of the logical signal (e.g., alogical input voltage applied to a gate of a transistor operating as aswitch), and the change in voltage from one state to another may not beinstantaneous. Rather, in some examples a voltage associated with alogical signal may follow a curve over time from one logical state toanother. Thus, the transitions shown in timing diagram 700 are notnecessarily indicative of an instantaneous transition. Further, theinitial state of a logical signal associated with a transition at anumbered operation may have been arrived during various times precedingthe numbered operation while still supporting the described transitionsand associated operations.

In accordance with embodiments of the present disclosure, the additionof a source following amplifier, such as those described with referenceto FIGS. 6 and 7, may improve robustness in detecting a logic state of amemory cell 105, and may also support relatively fast sensing whencertain operations are initiated in an overlapping or simultaneousmanner. However, the embodiment shown by example circuit 600 includessubstantially duplicated components (e.g., source follower amplifier640-a and source follower amplifier 640-b). These duplicated componentsmay have different properties as a result of manufacturing oroperational tolerances, and therefore the duplicated components may havedifferent effects on a signal of a signal line 280 as compared with asignal of a reference line 270. For example, a threshold voltage of atransistor of the source follower amplifier 640-a, V_(th,1), may not bethe same as a threshold voltage of a transistor of the source followeramplifier 640-b, V_(th,2), and thus a voltage drop from the signal line280-b to the source follower signal line 602 may be different from thevoltage drop between the reference line 270-b and the source followerreference line 604. Such a difference may impair the ability of thecircuit 600 to support robust read operations of the memory cell 105-c.For example, using the values of V_(sig) and V_(ref) described withreference to 710 and 711 of FIG. 7, if V_(th,1)=0.6V, and V_(th,2)=0.4V,V_(sig,SF,1) may be approximately 0.9V, V_(sig,SF,0) may beapproximately 0.6V and V_(ref,SF) may be approximately 0.95V. Thus,according to this given range of threshold voltages, both a logic 1 anda logic 0 may be sensed as a logic 0. Therefore, some embodiments inaccordance with the present disclosure may perform sensing operationswith a common component (e.g., a common source follower amplifier 640)to improve sensing operation robustness by eliminating such a source ofvariation.

FIG. 8 illustrates an example of a circuit 800 that may supportself-boost, source following, and sense-and-hold for accessing memorycells in accordance with various embodiments of the present disclosure.The circuit 800 includes a sense component 130-d for sensing a logicstate of a memory cell 105-d. Electrical signals may be communicatedbetween the sense component 130-d and the memory cell 105-d via a digitline 210-c, a signal line 280-c, a source follower line 802 which may,in combination, be referred to as a single access line of the memorycell 105-d. Signals of the access line may be illustrated by voltageV_(DL) on the digit line 210-b, V_(SL) on the signal line 280-b, andV_(SF) on the source follower signal line 602, as shown.

The circuit 800 may include a single source follower amplifier 640-ccoupled between the signal line 280-c and the source follower line 802,and a single source follower load component 645-b coupled between thesource follower signal line 802 and a voltage source 810-i having avoltage V₈, which may be enabled or disabled by a logical signal EQA.According to embodiments of the present disclosure, the source followerline 802 may support both a signal and a reference as stored and/orcompared at the sense component 130-d by way of sense-an-hold operationsdescribed herein. The circuit 800 may also include an amplifier 275-ccoupled between the digit line 210-c and the signal line 280-c, whichmay be enabled by voltage source 810-i. Thus, the memory cell 105-d mayrepresent a memory cell coupled between a first access line (e.g., thedigit line 210-b, the signal line 280-a, and the source follower line802) and a second access line (e.g., the word line 205-c). In theexample of circuit 800, the digit line 210-b, the signal line 280-a, andthe source follower line 802) may also represent a reference line.

The circuit 800 may also include a word line 205-c for selecting ordeselecting the memory cell 105-d (e.g., by way of logic signal WL), anda plate line 215-c for accessing a cell plate of a capacitor of thememory cell 105-d. In some examples the circuit 800 may also include awrite line 660-a, which may support various write operations, and mayprovide a connection or isolation between the sense component 130-d andthe digit line 210-c by enabling or disabling a switching component820-i (e.g., by activating or deactivating logical signal ISOW).

The circuit 800 may include a variety of voltage sources 810, which maybe coupled with various voltage supplies and/or common grounding orvirtual grounding points of a memory device that includes the examplecircuit 800.

A voltage source 810-a may represent a common grounding point (e.g., achassis ground, a neutral point, etc.), which may provide a commonreference voltage having a voltage V₀, from which other voltages aredefined. The voltage source 810-a may be coupled with the digit line210-b via the intrinsic capacitance 260-c of the digit line 210-c.

A voltage source 810-b having a voltage V₁ may represent a plate linevoltage source, and may be coupled with the memory cell 105-d via plateline 215-c of the memory cell 105-d.

A voltage source 810-c having a voltage V₂ may represent a digit linevoltage source, and may be coupled with the digit line 210-c via aswitching component 820-a, which may be activated or deactivated by alogical signal SW₁.

A voltage source 810-d having a voltage V₃ may represent a first signalline precharge voltage source, and may be coupled with the signal line280-c via a switching component 820-c, which may be activated ordeactivated by a logical signal SW₃.

A voltage source 810-h having a voltage V₇ may represent a second signalline precharge voltage source, and may be coupled with the signal line280-c via a switching component 820-f, which may be activated ordeactivated by a logical signal SW₈. In some examples, voltage source810-h may provide a reference voltage for sensing the logic state of thememory cell 105-d, such that V₇ is an average voltage between signalvoltage associated with sensing a logic 1 and a logic 0. In someexamples, voltage source 810-h may provide a sense voltage for a secondsensing of the memory cell 105-d, such that the sensing signal as aresult of applying V₇ to the signal line 280-c is an average voltagebetween signal voltage associated with sensing a logic 1 and a logic 0.

In some examples, a voltage of V₇ may be provided as a voltage droppedfrom a voltage supply of the memory device, which may be the samevoltage supply coupled with other voltage sources 810. For example, V₇may be provided by connecting voltage source 810-h with a same voltagesupply as voltage source 810-d, but with an intervening electrical load(e.g., a resistive load or capacitance) between the voltage supply andthe voltage source 810-h.

A voltage source 810-j having a voltage V₉ may represent a digit linevoltage source, and may be coupled with an amplifier 275-c which may bean example of the amplifiers 275 described with reference to FIGS. 2,4,and 6. For example, the amplifier 275-c may be a transistor, and thevoltage source 810-j may be coupled with the gate of the transistor. Theamplifier 275-c may be coupled with the signal line 280-c at a firstterminal, and the digit line 210-c at a second terminal. The amplifier275-c may provide a conversion of signals between the digit line 210-cand the signal line 280-c. For example, the amplifier 275-c may permit aflow of charge (e.g., electrical current) from the signal line 280-c tothe digit line 210-c, as fed or enabled by the voltage source 810-j,upon a reduction in voltage of the digit line 210-c (e.g., uponselection of the memory cell 105-d). A relatively small flow of chargeto the digit line 210-c may be associated with a relatively small changein voltage of the signal line 280-c, whereas a relatively large flow ofcharge to the digit line 210-c may be associated with a relatively largechange in voltage of the signal line 280-c. According to the netcapacitance of the signal line 280-c, for example, the signal line 280-cmay undergo a relatively small change in voltage or a relatively largechange in voltage depending on the flow of charge across the amplifier275-c after selecting the memory cell 105-c. In some examples theamplifier 275-c may be isolated from the digit line 210-c by a switchingcomponent 820-b, which may be activated or deactivated by a logicalsignal SW₂. The amplifier 275-c may also referred to as a “voltageregulator” or a “bias component,” relating to how the amplifier 275-cregulates a flow of charge in response to the voltage of the digit line210-c.

The circuit may also include a single integrator capacitor 830, whichmay be coupled with a variable voltage source 850. Integrator capacitor830 may be an example of the integrator capacitors 430 or 630 describedwith reference to FIGS. 4 and 6, and variable voltage source 850 may bean example of the variable voltage sources 450 or 650 described withreference to FIGS. 4 and 6. The integrator capacitor 830 may be coupledwith the signal line 280-c at a first terminal 831, and coupled with thevariable voltage source 850 at a second terminal 832.

In the example of circuit 800, the variable voltage source 850 mayinclude a voltage source 810-e having a voltage V₄ and a voltage source810-f having a voltage V₅, which may be selected for connection with theintegrator capacitor 830 by a switching component 820-d by way of alogical signal SW₄. In some examples the voltage source 810-e may becoupled with a common grounding point (not shown). In other examples thevoltage source 810-e may be coupled with a voltage supply that providesa positive or negative voltage. Voltage source 810-f may be coupled witha voltage supply having a higher voltage than that of voltage source810-e, thereby providing the boosting functions as described herein(e.g., in accordance with the difference in voltage between voltagesource 810-f and 810-e, equal to V₅−V₄, or simply V₅ when the voltagesource 810-e is grounded). Although a variable voltage source 850 isillustrated as including two voltage sources 810 and a switchingcomponent 820, a variable voltage source 850 supporting the operationsherein may include other configurations, such as a voltage buffer thatprovides a variable voltage to the second terminal 832 of the integratorcapacitor 830.

To support various operations described herein, the sense component130-d may be isolated from portions of the circuit 800. For example, thesense component 130-d may be coupled with the source follower line 802via a first switching component 820-g (e.g., an isolation component),which may be activated or deactivated by a logical signal ISO₁.Additionally or alternatively, the sense component 130-d may be coupledwith the source follower line 802 via a second switching component 820-h(e.g., an isolation component), which may be activated or deactivated bya logical signal ISO₂. Further, the sense component 130-d may be coupledwith a low voltage source and a high voltage source (not shown), whichmay be examples of sense component voltage sources 256-b and 265-cdescribed with reference to FIG. 2, respectfully. In accordance withembodiments of the present disclosure, sense component 130-d may includea sense amplifier that receives and compares a signal voltage (e.g., asstored or latched at a first terminal 131-d) with a reference voltage(e.g., as stored or latched at a second terminal 132-d).

Source follower amplifier 640-c be configured to support sourcefollowing in accordance with embodiments of the present disclosure. Forexample, source follower amplifier 640-c may be a transistor, and thesignal line 280-c may be coupled with a gate terminal of the transistor.The source follower amplifier 640-c may be fed by a voltage source 810-ghaving a voltage V₆, which may represent a source follower voltagesource. The voltage source 810-g may be coupled with the source followeramplifier 640-c via a switching component 820-e, which may be activatedor deactivated by a logical signal SW₅. Thus, logical signal SW₅ may beused to enable or disable the source follower amplifier 640-c forgenerating the signal source follower voltage V_(SF), where V_(SF) maybe equal to V_(SL) minus the threshold voltage of the transistor of thesource follower amplifier 640-c. Although example circuit 800 includesthe source follower amplifier 640-c, various other embodiments may omita source follower amplifier 640-c, and employ the features andoperations of self-boost and sample-and-hold in accordance withembodiments of the present disclosure without also employing sourcefollowing (e.g., with signal line 280-c being coupled with switchingcomponents 820-g and 820-h directly).

Each of the logical signals illustrated in circuit 800 may be providedby a memory controller (not shown), such as a memory controller 150described with reference to FIG. 1. In some examples, certain logicalsignals may be provided by other components. For example, logical signalWL may be provided by a row decoder (not shown), such as a row decoder125 described with reference to FIG. 1.

In various examples, voltage sources 800 may be coupled with differentconfigurations of voltage supplies and/or common grounding or virtualgrounding points of a memory device that includes the example circuit800. For example, in some embodiments voltage sources 810-a, 810-e,810-i, or any combination thereof, may be coupled with the same groundpoint or virtual ground point, and may provide substantially the samereference voltage for various operations of accessing the memory cell105-d. In some embodiments, several voltage sources 810 may be coupledwith the same voltage supply of a memory device. For example, in someembodiments, voltage sources 810-c, 810-d, and 810-g, or any combinationthereof, may be coupled with a voltage supply having a certain voltage(e.g., a voltage of 1.5V, which may be referred to as “VARY”). In suchembodiments, the signal line 280-c may be boosted to a voltagesubstantially equal to 2*VARY, or approximately 3.0V, prior to selectingthe memory cell 105-d via word line 205-c for sensing. Thus, inaccordance with embodiments of the present disclosure, self-boostoperations may overcome a need to provide a relatively higher voltagesupply for sense operations (e.g., a voltage source of 3.0V or more,which in some applications may refer to a “positive pump” voltage ofV_(pp)). In other examples, voltage source 810-f may be coupled with adifferent voltage supply than other voltage supplies (e.g., a voltage of1.2V, which may be referred to as “PDS”), which may thus be associatedwith a voltage boost of 1.2V. Although voltage sources 810 may becoupled with common voltage supplies and/or grounding points, thevoltage of each of the voltage sources 810 coupled with a common voltagesupply or common grounding point may be different due to differences inthe circuit (e.g., conductor length, width, resistance, capacitance,etc.) between the respective voltage sources 810 and the associatedcommon voltage supply or common grounding point.

FIG. 9 shows a timing diagram 900 illustrating operations of an exampleaccess procedure that may support self-boost, source following, andsample-and-hold for accessing memory cells in accordance with variousembodiments of the present disclosure. The example access procedure isdescribed with reference to components of the example circuit 800described with reference to FIG. 8.

In the example of timing diagram 900, voltage sources 810-a, 810-e, and810-i are considered to be grounded, and therefore at a zero voltage(e.g., V₀=0V, V₄=0V, and V₈=0V). However, in other examples voltagesources 810-a, 810-e, and 810-i may be at non-zero voltages, and thevoltages of timing diagram 900 may thus be adjusted accordingly. In someexamples, prior to initiating the operations of timing diagram 900, thedigit line 210-c and the plate line 215-c may be controlled to the samevoltage, which may minimize charge leakage across the memory cell 105-c.For example, according to the timing diagram 900, the digit line 210-chas an initial voltage of 0V, which may be the same as the initialvoltage of the plate line 215-c. In other examples, the digit line 210-cand the plate line 215-c may have some other initial voltage differentfrom the ground voltage.

At 901, the access procedure may include activating switching component820-d (e.g., by activating logical signal SW₆). Activating switchingcomponent 820-d may connect voltage source 810-h with the signal line280-c, and accordingly the voltage of signal line 280-c may rise tovoltage level V₇ as charge flows into the integrator capacitor 830. Inthe example of timing diagram 900, voltage level V₇ may represent areference voltage source, such that V₇ is an average voltage betweensignal voltage associated with sensing a logic 1 and a logic 0.Activating switching component 820-d may initiate a first prechargingoperation for the integrator capacitor 830. For example, at 901 theswitching component 820-f may be deactivated, such that the voltagesource 810-e (e.g., a ground or virtual ground voltage at 0V) is coupledwith the second terminal 832 of the integrator capacitor 830, and thevoltage source 810-h is coupled with the first terminal 831 of theintegrator capacitor 830. Thus, the integrator capacitor 830 may becharged according to the voltage difference between the voltage source810-h and the voltage source 810-e.

At 902, the access procedure may include deactivating the switchingcomponent 820-d (e.g., by deactivating logical signal SW₆). Deactivatingswitching component 820-d may isolate voltage source 810-h from thesignal line 280-c, and the voltage of signal line 280-c may hold atvoltage level V₇. Upon deactivating the switching component 820-d thesignal line 280-c, and thus the first terminal 831 of the integratorcapacitor 830, may be floating.

At 903, the access procedure may include activating switching component820-f (e.g., by activating logical signal SW₄). Activating switchingcomponent 820-f may cause a transition from the voltage source 810-ebeing coupled with the second terminal 832 of the integrator capacitor830 to the voltage source 810-f being coupled with the second terminal832 of the integrator capacitor 830. By connecting the second terminal832 of the integrator capacitor 830 to a voltage source at a highervoltage, the charge stored by the integrator capacitor 830 may beboosted to a higher voltage, and accordingly the voltage of signal line280-c, coupled with the first terminal 831 of the integrator capacitor830, may rise to voltage level (V₇+V₃). Thus, activating switchingcomponent 820-f may initiate a first boosting operation for theintegrator capacitor 830.

At 904, the access procedure may include deactivating switchingcomponent 820-f (e.g., by deactivating logical signal SW₄). Deactivatingswitching component 820-f may cause a transition from the voltage source810-f being coupled with the second terminal 832 of the integratorcapacitor 830 to the voltage source 810-e being coupled with the secondterminal 832 of the integrator capacitor 830. By connecting the secondterminal 832 of the integrator capacitor 830 to the voltage source at alower voltage, the charge stored by the integrator capacitor 830 may beshifted to a lower voltage, and accordingly the voltage of signal line280-c, coupled with the first terminal 831 of the integrator capacitor830, may drop by voltage level of V₅−V₄ (or just V₅ in the event thatvoltage source 810-e is coupled with a common ground point). Thus,deactivating switching component 820-f may initiate a first shiftingoperation for the integrator capacitor 830. In examples that do notemploy source following, the shifting may reduce the voltage of thesignal line 280-c to a level that may be read by the sense component130-d (e.g., a voltage between low and high voltage sources of the sensecomponent 130-d, not shown).

Although operations at 903 and 904 are included in the example of timingdiagram 900, in some examples these steps may be omitted. In otherwords, when generating a reference signal first in a sensing operationthat employs sample-and-hold techniques, it may be unnecessary toperform boost and shift operations to generate the reference.

At 905, the access procedure may include enabling the source followeramplifier 640-c coupled between the signal line 280-c and the sourcefollower line 802. For example, the source follower amplifier 640-c maybe a transistor, and enabling the source follower amplifier 640-c mayinclude connecting a source of the transistor with voltage source 810-g,having a voltage V₆, by enabling the switching component 820-e (e.g., byactivating logical signal SW₅). Connecting the source follower amplifier640-c with the voltage source 810-g may support charge flowing throughthe source follower amplifier 640-c from the signal line 280-c to thesource follower line 802, and also an amplified charge (e.g., a multipleof the charge flowing from the signal line 280-c) flowing through thesource follower amplifier 640-c from the voltage source 810-g to thesource follower line 802. Accordingly, charge may accumulate on thesource follower line 802 until the voltage threshold of the transistoris no longer exceeded. In other words, the voltage of the sourcefollower line 802 may rise to a level of V_(SF)=(V_(SL)−V_(th)), whereV_(th) is the threshold voltage of the transistor of the source followeramplifier 640-c.

In some examples the voltage of the signal line 280-c may only drop by anegligible amount upon enabling the source follower amplifier 640-c,because only a trivial amount of charge flows from the signal line 280-cto the source follower line 802. Although the voltage of the sourcefollower line 802 may be lower than the voltage of the signal line280-c, the increased amount of charge provided to the source followerline 802 may support larger components in the sense component 130-d, andmay also limit charge sharing between the signal line 280-c and thesense component 130-d.

In some examples, the source follower load component 645-c may also beenabled during the operations of 905. In examples where the sourcefollower load component 645-c is a transistor, signal EQA may be enabledat the gate of the transistor, which may support current flowing throughthe source follower amplifier 640-c to also flow through the sourcefollower load component 645-c. Thus, in some examples the sourcefollower load component 645-c may operate as a current generator tosupport source following functionality. Although signal EQA may besubstantially a digital signal having a relatively high voltage suchthat a transistor of the source follower load component 645-c operatesin a saturation region, signal EQA may also be selected such that atransistor of the source follower load component 645-c operates in alinear, or ohmic region. In other words, signal EQA may be selected inorder to operate the source follower load component 645-c at aparticular working point. Further, although signal EQA may be enabledduring source follower operations of 905, signal EQA may be disabled atother times (e.g., prior to 905, or after developing V_(ref,SF)), whichmay reduce energy consumption.

At 906, the access procedure may include isolating the second node 132-dof the sense component 130-d from the source follower line 802 bydeactivating switching component 820-h (e.g., by deactivating logicalsignal ISO₂). Isolating the sense component 130-c from the sourcefollower line 802 may allow the sense component 130-c to store (e.g.,“hold”) a reference voltage and/or charge associated with the sourcefollower line voltage at the second terminal 132-d of the sensecomponent 130-d prior to determining the logic state stored in thememory cell 105-d.

At 907, the access procedure may include disabling the source followeramplifier 640-c. For example, disabling the source follower amplifier640-c may include disconnecting the source of the transistor fromvoltage source 810-g by disabling the switching component 820-e (e.g.,by deactivating logical signal SW₅). Disabling the source followeramplifier 640-c may, for example, reduce power consumption as comparedwith embodiments where the source follower amplifier 640-c remainsenabled. In some examples the source follower load component 645-c mayalso be disabled before or after 907 (e.g., by deactivating signal EQA),which may reduce power consumption as compared with embodiments wherethe source follower load component 645-c remains enabled.

At 908, the access procedure may include activating switching component820-c (e.g., by activating logical signal SW₃). Activating switchingcomponent 820-c may connect voltage source 810-d with the signal line280-c, and accordingly the voltage of signal line 280-c may rise tovoltage level V₃ as charge flows into the integrator capacitor 830.Thus, activating switching component 820-c may initiate a secondprecharging operation for the integrator capacitor 830. For example, at910 the switching component 820-f may be deactivated, such that thevoltage source 810-e (e.g., a ground or virtual ground voltage at 0V) iscoupled with the second terminal 832 of the integrator capacitor 830,and the voltage source 810-d is coupled with the first terminal 831 ofthe integrator capacitor 830. Thus, the integrator capacitor 830 may becharged according to the voltage difference between the voltage source810-d and the voltage source 810-e.

At 909, the access procedure may include activating switching component820-b (e.g., by activating logical signal SW₂). Activating switchingcomponent 820-b may initiate a precharging operation for the digit line210-c. For example, activating switching component 820-b may connect thesignal line 280-c with the digit line 210-c, which may be coupled withthe voltage source 810-a (e.g., a ground or virtual ground voltage) byway of the intrinsic capacitance 260-c. As fed by the voltage source810-d, charge may flow through the amplifier 275-c and build on thedigit line 210-c, causing the voltage on the digit line 210-c to rise.The voltage of the digit line 210-c may rise until the threshold voltageof the amplifier 275-c (e.g., threshold voltage V_(th,amp)) is no longerexceeded. Thus, after activating switching component 820-b, the voltageof the digit line 210-c may rise to a voltage level of V₉−V_(th,amp) ascharge flows from the signal line 280-c (e.g., as fed by the voltagesource 810-d), and the digit line 210-c, including intrinsic capacitance260-c, may be charged according to the voltage difference between thevoltage level V₉−V_(th,amp) and the voltage source 810-a (e.g., 0V). Insome examples, the voltage level V₉ may be selected such that the digitline 210-c is precharged to substantially the same level as the signalline 280-c. For example, the voltage level V₉ may be set at a level ofV₃+V_(th,amp), which may be provided by a voltage supply having avoltage level greater than voltage source 810-d. Thus, in some examplesthe digit line 210-c may rise to a voltage level equal to voltage levelV₃ in response to activating switching component 820-b at 909.

Additionally or alternatively, in some examples the digit line 210-c maybe precharged by the voltage source 810-c. For example, prior toactivating switching component 820-b, the access procedure 900 mayinclude activating switching component 820-a (e.g., by activatinglogical signal SW₁). Activating switching component 820-a may initiatean alternative precharging operation for the digit line 210-c that isnot shown in timing diagram 900. As fed by the voltage source 810-c,charge may build on the digit line 210-c, causing the voltage on thedigit line 210-c to match the voltage level V₂. In some examples thevoltage level V₂ may be substantially equal to the voltage level V₃,such that the digit line 210-c and the signal line 280-c are prechargedto the same voltage prior to activating switching component 820-b. Insome examples, precharging the digit line 210-c with the voltage source810-c may reduce power consumption and/or reduce precharge timeassociated with accessing the memory cell 105-d. Following a prechargeof the digit line 210-c by the voltage source 810-c, the accessprocedure may include activating switching component 820-b (e.g., byactivating logical signal SW₂) to connect the signal line 280-c to thedigit line 210-c.

At 910, the access procedure may include deactivating the switchingcomponent 820-c (e.g., by deactivating logical signal SW₃). Deactivatingswitching component 820-c may isolate voltage source 810-d from thesignal line 280-c, and the voltage of signal line 280-c may hold atvoltage level V₃. Upon deactivating the switching component 820-c thereference line 280-c, and thus the first terminal 831 of the integratorcapacitor 830, may be floating, and the signal line 280-c may maintain alevel of charge according to the capacitance of the signal line 280-c,including the capacitance of the integrator capacitor 830.

At 911, the access procedure may include activating switching component820-f (e.g., by activating logical signal SW₄). Activating switchingcomponent 820-f may cause a transition from the voltage source 810-ebeing coupled with the second terminal 832 of the integrator capacitor830 to the voltage source 810-f being coupled with the second terminal832 of the integrator capacitor 830. By connecting the second terminal832 of the integrator capacitor 830 to a voltage source at a highervoltage, the charge stored by the integrator capacitor 830 may again beboosted to a higher voltage, and accordingly the voltage of signal line280-c, coupled with the first terminal 831 of the integrator capacitor830, may rise to voltage level (V₃+V₅). Thus, activating switchingcomponent 820-f may initiate a second boosting operation for theintegrator capacitor 830.

At 912, the access procedure may include selecting the memory cell 105-d(e.g., by activating a word line via logical signal WL). Selecting thememory cell 105-d may cause a capacitor of the memory cell 105-d to becoupled with the digit line 210-c. Accordingly, charge may be sharedbetween the memory cell 105-d, the digit line 210-c, and the signal line280-c, which may depend on the logic state (e.g., the charge and/orpolarization) stored in the memory cell 105-d.

For example, when the memory cell 105-d stores a logic 1, the capacitorof the memory cell 105-d may store a positive charge by way of apositive polarization (e.g., a charge state 305-a as described withreference to FIG. 3). Thus, when memory cell 105-d storing a logic 1 isselected, a relatively small amount of charge may flow from the digitline 210-c to the memory cell 105-d. As charge flows from the digit line210-c to the memory cell 105-d, the voltage of the digit line 210-c maydrop, which may allow the threshold voltage of the amplifier 275-c to beexceeded. When the threshold voltage of the amplifier 275-c is exceeded,charge may flow from the signal line 280-c (e.g., from the integratorcapacitor 830) to the digit line 210-c across the amplifier 275-c, aswell as a relatively small amount of charge from the voltage source810-j, depending on the characteristics of the amplifier 275-c.Accordingly, charge may flow to the digit line 210-c until the voltageof the digit line 210-c returns to the voltage level equal toV₉−V_(th,amp). When selecting the memory cell 105-d storing a logic 1,because a relatively small amount of charge flows into the memory cell105-d, the signal line 280-c may undergo a relatively small voltage dropafter selecting the memory cell 105-d, illustrated by the voltage ofV_(SL,1).

Alternatively, when the memory cell 105-d stores a logic 0, thecapacitor of the memory cell 105-d may store a negative charge by way ofa negative polarization (e.g., charge state 310-a as described withreference to FIG. 3). Thus, when memory cell 105-d storing a logic 0 isselected, a relatively large amount of charge may flow from the digitline 210-c to the memory cell 105-d. Accordingly, the signal line 280-cmay undergo a relatively larger voltage drop, illustrated by the voltageof V_(SL,0), as charge flows through the amplifier 275-c to return thedigit line to the voltage level V₉−V_(th,amp), such that the thresholdvoltage V_(th,amp) of the amplifier 275-b is no longer exceeded. In someexamples, selecting the memory cell 105-d storing a logic 0 may resultin a partial loss of polarization of a capacitor of the memory cell105-d. In examples where a 2Pr sensing operation is employed, selectingthe memory cell 105-d storing a logic 0 may result in a reversal ofsaturation polarization of the capacitor of the memory cell 105-d, suchthat an amount of charge associated with twice the saturationpolarization flows into the memory cell 105-d. In either case, selectinga memory cell 105-d storing a logic 0 according to the present examplemay require a subsequent refresh or rewrite operation.

At 913, the access procedure may include isolating the digit line 210-cfrom the signal line 280-c by deactivating the switching component 820-b(e.g., by deactivating logical signal SW₂). Isolating the digit line210-c from the signal line 280-c may prevent additional charge frombeing shared between the digit line 210-c and the signal line 280-c,including charge sharing across the amplifier 275-c that may be causedby the threshold voltage of the amplifier 275-c being exceeded as aresult of subsequent sensing operations.

At 914, the access procedure may include deactivating switchingcomponent 820-f (e.g., by deactivating logical signal SW₄). Deactivatingswitching component 820-f may cause a transition from the voltage source810-f being coupled with the second terminal 832 of the integratorcapacitor 830 to the voltage source 810-e being coupled with the secondterminal 832 of the integrator capacitor 830. By connecting the secondterminal 832 of the integrator capacitor 830 to the voltage source at alower voltage, the charge stored by the integrator capacitor 830 may beshifted to a lower voltage, and accordingly the voltage of signal line280-c, coupled with the first terminal 831 of the integrator capacitor830, may drop by voltage level of V₅−V₄ (or just V₅ in the event thatvoltage source 810-e is coupled with a common ground point). Thus,deactivating switching component 820-f may initiate a second shiftingoperation for the integrator capacitor 830. In embodiments that do notemploy source following, the shifting may reduce the voltage of thesignal line 280-c to a level that may be read by the sense component130-d (e.g., a voltage between low and high voltage sources of the sensecomponent 130-d, not shown).

At 915 the access procedure may include enabling the source followeramplifier 640-c coupled between the signal line 280-c and the sourcefollower line 802. Enabling the source follower amplifier 640-c mayinclude connecting a source of the transistor with voltage source 810-gfor a second time by enabling the switching component 820-e (e.g., byactivating logical signal SW₅). Connecting the source follower amplifier640-c with the voltage source 810-g may again support charge flowingthrough the source follower amplifier 640-c from the signal line 280-cto the source follower line 802, and also an amplified charge (e.g., amultiple of the charge flowing from the signal line 280-c) flowingthrough the source follower amplifier 640-c from the voltage source810-g to the source follower line 802. Accordingly, charge mayaccumulate on the source follower line 802 until the voltage thresholdof the transistor is no longer exceeded. In other words, the voltage ofthe source follower line 802 may rise to a level ofV_(SF)=(V_(SL)−V_(th)), where in this case V_(SL) is based on selectingthe memory cell 105-d.

In some examples, the source follower load component 645-c may also beenabled during the operations of 915. In examples where the sourcefollower load component 645-c is a transistor, signal EQA may again beenabled at the gate of the transistor, which may support current flowingthrough the source follower amplifier 640-c to also flow through thesource follower load component 645-c. Although signal EQA may be enabledor reenabled during source follower operations of 915, signal EQA may bedisabled at other times (e.g., between 905 and 915, or after developingV_(sig,SF)), which may reduce energy consumption.

At 916 the access procedure may include isolating the first terminal131-d of the sense component 130-d from the source follower line 802 bydeactivating switching component 820-g (e.g., by deactivating logicalsignal ISO₁). Isolating the first terminal 131-d of the sense component130-d from the source follower line 802 may allow the sense component130-d to store (e.g., “hold”) a voltage and/or charge associated withthe source follower line voltage at the first terminal 131-d of thesense component 130-c prior to determining the logic state stored in thememory cell 105-c.

At 917 the access procedure may include detecting a difference betweenthe stored voltages at the first and second terminals of the sensecomponent 130-d. For example, if the signal stored at the first terminalis greater than the signal stored at the second terminal (e.g.,V_(sig,SF,1)>V_(ref,SF)), the sense component 130-d may output a voltageequal to the high voltage source of the sense component. If the signalstored at the first terminal is less than the signal stored at thesecond terminal (e.g., V_(sig,SF,0)<V_(ref,SF)), the sense component130-d may output a voltage equal to the low voltage source of the sensecomponent.

Although illustrated as separate operations occurring at differenttimes, certain operations may occur simultaneously, or in a differentorder. In some examples, various operations may be advantageouslyinitiated simultaneously in order to reduce the amount of time requiredto sense a logic state of the memory cell 105-d. For example, connectingthe digit line 210-b with the signal line 280-b at 911 may occur priorto the precharging at 910, or these operations may occur simultaneously.

The order of operations shown in timing diagram 900 is for illustrationonly, and various other orders and combinations of steps may beperformed to support self-boost in accordance with the presentdisclosure. Further, the timing of the operations of timing diagram 900is also for illustration purposes only, and is not meant to indicate aparticular relative duration between one operation and another. Variousoperations may occur over a duration that is relatively shorter orrelatively longer than illustrated in various embodiments of self-boostin accordance with the present disclosure.

The transitions of the logical signals of the timing diagram 900 areillustrative of transitions from one state to another, and generallyreflect transitions between an enabled or activated state (e.g., state“1”) and a disabled or deactivated state (e.g., state “0”) as associatedwith a particular numbered operation. In various examples the states maybe associated with a particular voltage of the logical signal (e.g., alogical input voltage applied to a gate of a transistor operating as aswitch), and the change in voltage from one state to another may not beinstantaneous. Rather, in some examples a voltage associated with alogical signal may follow a curve over time from one logical state toanother. Thus, the transitions shown in timing diagram 700 are notnecessarily indicative of an instantaneous transition. Further, theinitial state of a logical signal associated with a transition at anumbered operation may have been arrived during various times precedingthe numbered operation while still supporting the described transitionsand associated operations.

In accordance with embodiments of the present disclosure, the featuresand operations of sample-and-hold may reduce or eliminate some sourcesof variation when sensing a memory cell 105. In some examples it may befurther advantageous to perform a second selection of a memory cell 105to generate a reference, rather than predetermine a reference voltagesource. Thus, some embodiments in accordance with the present disclosuremay perform a self-referencing sample-and-hold operations to furtherimprove sensing robustness.

FIG. 10 shows a timing diagram 1000 illustrating operations of anexample access procedure that may support self-boost, source following,and a self-referencing sample-and-hold for accessing memory cells inaccordance with various embodiments of the present disclosure. Theexample access procedure is described with reference to components ofthe example circuit 800 described with reference to FIG. 8.

In the example of timing diagram 1000, voltage sources 810-a, 810-e, and810-i are considered to be grounded, and therefore at a zero voltage(e.g., V₀=0V, V₄=0V, and V₈=0V). However, in other examples voltagesources 810-a, 810-e, and 810-i may be at non-zero voltages, and thevoltages of timing diagram 1000 may thus be adjusted accordingly. Insome examples, prior to initiating the operations of timing diagram1000, the digit line 210-c and the plate line 215-c may be controlled tothe same voltage, which may minimize charge leakage across the memorycell 105-c. For example, according to the timing diagram 1000, the digitline 210-c has an initial voltage of 0V, which may be the same as theinitial voltage of the plate line 215-c. In other examples, the digitline 210-c and the plate line 215-c may have some other initial voltagedifferent from the ground voltage.

At 1001, the access procedure may include activating switching component820-c (e.g., by activating logical signal SW₃). Activating switchingcomponent 820-c may connect voltage source 810-d with the signal line270-b, and accordingly the voltage of signal line 280-c may rise tovoltage level V₃ as charge flows into the integrator capacitor 830.Thus, activating switching component 820-c may initiate a firstprecharging operation for the integrator capacitor 830. For example, at1001 the switching component 820-f may be deactivated, such that thevoltage source 810-e (e.g., a ground or virtual ground voltage at 0V) iscoupled with the second terminal 832 of the integrator capacitor 830,and the voltage source 810-d is coupled with the first terminal 831 ofthe integrator capacitor 830. Thus, the integrator capacitor 830 may becharged according to the voltage difference between the voltage source810-d and the voltage source 810-e.

At 1002, the access procedure may include activating switching component820-b (e.g., by activating logical signal SW₂). Activating switchingcomponent 820-b may initiate a first precharging operation for the digitline 210-c. For example, activating switching component 820-b mayconnect the signal line 280-c with the digit line 210-c, which may becoupled with the voltage source 810-a (e.g., a ground or virtual groundvoltage) by way of the intrinsic capacitance 260-c. As fed by thevoltage source 810-d, charge may flow through the amplifier 275-c andbuild on the digit line 210-c, causing the voltage on the digit line210-c to rise. The voltage of the digit line 210-c may rise until thethreshold voltage of the amplifier 275-c (e.g., threshold voltageV_(th,amp)) is no longer exceeded. Thus, after activating switchingcomponent 820-b, the voltage of the digit line 210-c may rise to avoltage level of V₉−V_(th,amp) as charge flows from the signal line280-c (e.g., as fed by the voltage source 810-d), and the digit line210-c, including intrinsic capacitance 260-c, may be charged accordingto the voltage difference between the voltage level V₉−V_(th,amp) andthe voltage source 810-a (e.g., 0V). In some examples, the voltage levelV₉ may be selected such that the digit line 210-c is precharged tosubstantially the same level as the signal line 280-c. For example, thevoltage level V₉ may be set at a level of V₃+V_(th,amp), which may beprovided by a voltage supply having a voltage level greater than voltagesource 810-d. Thus, in some examples the digit line 210-c may rise to avoltage level equal to voltage level V₃ in response to activatingswitching component 820-b at 1002.

Additionally or alternatively, in some examples the digit line 210-c maybe precharged by the voltage source 810-c. For example, prior toactivating switching component 820-b, the access procedure 1000 mayinclude activating switching component 820-a (e.g., by activatinglogical signal SW₁). Activating switching component 820-a may initiatean alternative precharging operation for the digit line 210-c that isnot shown in timing diagram 1000. As fed by the voltage source 810-c,charge may build on the digit line 210-c, causing the voltage on thedigit line 210-c to match the voltage level V₂. In some examples thevoltage level V₂ may be substantially equal to the voltage level V₃,such that the digit line 210-c and the signal line 280-c are prechargedto the same voltage prior to activating switching component 820-b. Insome examples, precharging the digit line 210-c with the voltage source810-c may reduce power consumption and/or reduce precharge timeassociated with accessing the memory cell 105-d. Following a prechargeof the digit line 210-c by the voltage source 810-c, the accessprocedure may include activating switching component 820-b (e.g., byactivating logical signal SW₂) to connect the signal line 280-c to thedigit line 210-c.

At 1003, the access procedure may include deactivating the switchingcomponent 820-c (e.g., by deactivating logical signal SW₃). Deactivatingswitching component 820-c may isolate voltage source 810-d from thesignal line 280-c, and the voltage of signal line 280-c may hold atvoltage level V₃. Upon deactivating the switching component 820-c thereference line 280-c, and thus the first terminal 831 of the integratorcapacitor 830, may be floating.

At 1004, the access procedure may include activating switching component820-f (e.g., by activating logical signal SW₄). Activating switchingcomponent 820-f may cause a transition from the voltage source 810-ebeing coupled with the second terminal 832 of the integrator capacitor830 to the voltage source 810-f being coupled with the second terminal832 of the integrator capacitor 830. By connecting the second terminal832 of the integrator capacitor 830 to a voltage source at a highervoltage, the charge stored by the integrator capacitor 830 may beboosted to a higher voltage, and accordingly the voltage of signal line280-c, coupled with the first terminal 831 of the integrator capacitor830, may rise to voltage level (V₃+V₅). Thus, activating switchingcomponent 820-f may initiate a first boosting operation for theintegrator capacitor 830.

At 1005, the access procedure may include selecting the memory cell105-d (e.g., by activating a word line via logical signal WL). Selectingthe memory cell 105-d may cause a capacitor of the memory cell 105-d tobe coupled with the digit line 210-c. Accordingly, charge may be sharedbetween the memory cell 105-d, the digit line 210-c, and the signal line280-c, which may depend on the logic state (e.g., the charge and/orpolarization) stored in the memory cell 105-d.

For example, when the memory cell 105-d stores a logic 1, the capacitorof the memory cell 105-d may store a positive charge by way of apositive polarization (e.g., a charge state 305-a as described withreference to FIG. 3). Thus, when memory cell 105-d storing a logic 1 isselected, a relatively small amount of charge may flow from the digitline 210-c to the memory cell 105-d. As charge flows from the digit line210-c to the memory cell 105-d, the voltage of the digit line 210-c maydrop, which may allow the threshold voltage of the amplifier 275-c to beexceeded. When the threshold voltage of the amplifier 275-c is exceeded,charge may flow from the signal line 280-c (e.g., from the integratorcapacitor 830) to the digit line 210-c across the amplifier 275-c, aswell as a relatively small amount of charge from the voltage source810-j, depending on the characteristics of the amplifier 275-c.Accordingly, charge may flow to the digit line 210-c until the voltageof the digit line 210-c returns to the voltage level equal toV₉−V_(th,amp). When selecting the memory cell 105-d storing a logic 1,because a relatively small amount of charge flows into the memory cell105-d, the signal line 280-c may undergo a relatively small voltage dropafter selecting the memory cell 105-d, illustrated by the voltage ofV_(SL,1).

Alternatively, when the memory cell 105-d stores a logic 0, thecapacitor of the memory cell 105-d may store a negative charge by way ofa negative polarization (e.g., charge state 310-a as described withreference to FIG. 3). Thus, when memory cell 105-d storing a logic 0 isselected, a relatively large amount of charge may flow from the digitline 210-c to the memory cell 105-d. Accordingly, the signal line 280-cmay undergo a relatively larger voltage drop, illustrated by the voltageof V_(SL,0), as charge flows through the amplifier 275-c to return thedigit line to the voltage level V₉−V_(th,amp), such that the thresholdvoltage V_(th,amp) of the amplifier 275-b is no longer exceeded. In someexamples, selecting the memory cell 105-d storing a logic 0 may resultin a partial loss of polarization of a capacitor of the memory cell105-d. In examples where a 2Pr sensing operation is employed, selectingthe memory cell 105-d storing a logic 0 may result in a reversal ofsaturation polarization of the capacitor of the memory cell 105-d, suchthat an amount of charge associated with twice the saturationpolarization flows into the memory cell 105-d. In either case, selectinga memory cell 105-d storing a logic 0 according to the present examplemay require a subsequent refresh or rewrite operation.

At 1006, the access procedure may include isolating the digit line 210-cfrom the signal line 280-c by deactivating the switching component 820-b(e.g., by deactivating logical signal SW₂). Isolating the digit line210-c from the signal line 280-c may prevent additional charge frombeing shared between the digit line 210-c and the signal line 280-c,including charge sharing across the amplifier 275-c that may be causedby the threshold voltage of the amplifier 275-c being exceeded as aresult of subsequent sensing operations.

At 1007, the access procedure may include deactivating switchingcomponent 820-f (e.g., by deactivating logical signal SW₄). Deactivatingswitching component 820-f may cause a transition from the voltage source810-f being coupled with the second terminal 832 of the integratorcapacitor 830 to the voltage source 810-e being coupled with the secondterminal 832 of the integrator capacitor 830. By connecting the secondterminal 832 of the integrator capacitor 830 to the voltage source at alower voltage, the charge stored by the integrator capacitor 830 may beshifted to a lower voltage, and accordingly the voltage of signal line280-c, coupled with the first terminal 831 of the integrator capacitor830, may drop by voltage level of V₅−V₄ (or just V₅ in the event thatvoltage source 810-e is coupled with a common ground point). Thus,deactivating switching component 820-f may initiate a first shiftingoperation for the integrator capacitor 830. In embodiments that do notemploy source following, the shifting may reduce the voltage of thesignal line 280-c to a level that may be read by the sense component130-d (e.g., a voltage between low and high voltage sources of the sensecomponent 130-d, not shown).

At 1008 the access procedure may include enabling the source followeramplifier 640-c coupled between the signal line 280-c and the sourcefollower line 802. Enabling the source follower amplifier 640-c mayinclude connecting a source of the transistor with voltage source 810-gfor a second time by enabling the switching component 820-e (e.g., byactivating logical signal SW₅). Connecting the source follower amplifier640-c with the voltage source 810-g may support charge flowing throughthe source follower amplifier 640-c from the signal line 280-c to thesource follower line 802, and also an amplified charge (e.g., a multipleof the charge flowing from the signal line 280-c) flowing through thesource follower amplifier 640-c from the voltage source 810-g to thesource follower line 802. Accordingly, charge may accumulate on thesource follower line 802 until the voltage threshold of the transistoris no longer exceeded. In other words, the voltage of the sourcefollower line 802 may rise to a level of V_(SF)=(V_(SL)−V_(th)), wherein this case V_(SL) is based on selecting the memory cell 105-d.

In some examples, the source follower load component 645-c may also beenabled during the operations of 1008. In examples where the sourcefollower load component 645-c is a transistor, signal EQA may be enabledat the gate of the transistor, which may support current flowing throughthe source follower amplifier 640-c to also flow through the sourcefollower load component 645-c. Thus, in some examples the sourcefollower load component 645-c may operate as a current generator tosupport source following functionality. Although signal EQA may besubstantially a digital signal having a relatively high voltage suchthat a transistor of the source follower load component 645-c operatesin a saturation region, signal EQA may also be selected such that atransistor of the source follower load component 645-c operates in alinear, or ohmic region. In other words, signal EQA may be selected inorder to operate the source follower load component 645-c at aparticular working point. Further, although signal EQA may be enabledduring source follower operations of 1008, signal EQA may be disabled atother times (e.g., prior to 1008, or after developing V_(sig,SF)), whichmay reduce energy consumption.

At 1009 the access procedure may include isolating the first terminal131-d of the sense component 130-d from the source follower line 802 bydeactivating switching component 820-g (e.g., by deactivating logicalsignal ISO₁). Isolating the first terminal 131-d of the sense component130-d from the source follower line 802 may allow the sense component130-d to store (e.g., “hold”) a voltage and/or charge associated withthe source follower line voltage at the first terminal 131-d of thesense component 130-c prior to determining the logic state stored in thememory cell 105-c.

At 1010, the access procedure may include disabling the source followeramplifier 640-c. For example, disabling the source follower amplifier640-c may include disconnecting the source of the transistor fromvoltage source 810-g by disabling the switching component 820-e (e.g.,by deactivating logical signal SW₅). Disabling the source followeramplifier 640-c may, for example, reduce power consumption as comparedwith embodiments where the source follower amplifier 640-c remainsenabled. In some examples the source follower load component 645-c mayalso be disabled before or after 907 (e.g., by deactivating signal EQA),which may reduce power consumption as compared with embodiments wherethe source follower load component 645-c remains enabled.

At 1011, the access procedure may include activating switching component820-d (e.g., by activating logical signal SW₆). Activating switchingcomponent 820-d may connect voltage source 810-h with the signal line280-c, and accordingly the voltage of signal line 280-c may rise tovoltage level V₇ as charge flows into the integrator capacitor 830. Inthe example of timing diagram 1000, voltage level V₇ provide a sensevoltage for a second sensing of the memory cell 105-d, such that thesignal as a result of applying V₇ to the signal line 280-c is an averagevoltage between signal voltage associated with initially sensing a logic1 and a logic 0. Activating switching component 820-d may initiate asecond precharging operation for the integrator capacitor 830. Forexample, at 1013 the switching component 820-f may be deactivated, suchthat the voltage source 810-e (e.g., a ground or virtual ground voltageat 0V) is coupled with the second terminal 832 of the integratorcapacitor 830, and the voltage source 810-h is coupled with the firstterminal 831 of the integrator capacitor 830. Thus, the integratorcapacitor 830 may be charged according to the voltage difference betweenthe voltage source 810-h and the voltage source 810-e.

At 1012, the access procedure may include activating switching component820-b (e.g., by activating logical signal SW₂) for a second time.Activating switching component 820-b may initiate a second prechargingoperation for the digit line 210-c. The voltage of the digit line 210-cmay rise until the threshold voltage of the amplifier 275-c (e.g.,threshold voltage V_(th,amp)) is no longer exceeded, which in someexamples may not result from a net transfer of charge (e.g., then thevoltage of the digit line 210-c is held between 1006 and 1014. Thus,after activating switching component 820-b, the digit line 210-c,including intrinsic capacitance 260-c, may again be charged according tothe voltage difference between the voltage level V₉−V_(th,amp) and thevoltage source 810-a (e.g., 0V).

At 1013, the access procedure may include deactivating the switchingcomponent 820-d (e.g., by deactivating logical signal SW₆). Deactivatingswitching component 820-d may isolate voltage source 810-h from thesignal line 280-c, and the voltage of signal line 280-c may hold atvoltage level V₇. Upon deactivating the switching component 820-d thesignal line 280-c, and thus the first terminal 831 of the integratorcapacitor 830, may be floating.

At 1014, the access procedure may include activating switching component820-f (e.g., by activating logical signal SW₄). Activating switchingcomponent 820-f may cause a transition from the voltage source 810-ebeing coupled with the second terminal 832 of the integrator capacitor830 to the voltage source 810-f being coupled with the second terminal832 of the integrator capacitor 830. By connecting the second terminal832 of the integrator capacitor 830 to a voltage source at a highervoltage, the charge stored by the integrator capacitor 830 may beboosted to a higher voltage, and accordingly the voltage of signal line280-c, coupled with the first terminal 831 of the integrator capacitor830, may rise to voltage level (V₇+V₃). Thus, activating switchingcomponent 820-f may initiate a second boosting operation for theintegrator capacitor 830.

At 1015, the access procedure may include selecting the memory cell105-d (e.g., by activating a word line via logical signal WL) for asecond time. Selecting the memory cell 105-d for a second time may causea capacitor of the memory cell 105-d to again be coupled with the digitline 210-c. Accordingly, charge may be shared between the memory cell105-d, the digit line 210-c, and the signal line 280-c, which may dependon the logic state (e.g., the charge and/or polarization) stored in thememory cell 105-d.

For example, in a 2Pr sensing scheme, accessing the memory cell 105-dfor the first time may result in the memory cell 105-d memory cellstoring an intermediate logic state, such as an intermediate logic 1,regardless of whether the memory cell 105-d originally stored a logic 1or 0. This may be a result of the voltage and/or charge applied whenselecting the memory cell 105-d at 1005, where for a logic 1 the appliedvoltage and/or charge may only provide a displacement component, and fora logic 0 the applied voltage and/or charge may provide both adisplacement component and a polarization component that may reverse thepolarization of a capacitor of the memory cell 105-d. In either case,when memory cell 105-d is selected s second time, a relatively smallamount of charge may flow from the digit line 210-c to the memory cell105-d due to storing the intermediate logic 1, and accordingly, thesignal line 280-c may undergo a relatively small voltage drop afterselecting the memory cell 105-d. In some examples, in order to generatea reference signal from selecting the memory cell a second time at 1016,the applied voltage (e.g., V₇+V₃) may be selected such that the signalline voltage when selecting the memory cell a second time is between thesignal line voltage when initially selecting a memory cell that stores alogic 1 and the signal line voltage when initially selecting a memorycell that stores a logic 0.

At 1016, the access procedure may include isolating the digit line 210-cfrom the signal line 280-c by deactivating the switching component 820-b(e.g., by deactivating logical signal SW₂). Isolating the digit line210-c from the signal line 280-c may prevent additional charge frombeing shared between the digit line 210-c and the signal line 280-c,including charge sharing across the amplifier 275-c that may be causedby the threshold voltage of the amplifier 275-c being exceeded as aresult of subsequent sensing operations.

At 1017, the access procedure may include deactivating switchingcomponent 820-f (e.g., by deactivating logical signal SW₄). Deactivatingswitching component 820-f may cause a transition from the voltage source810-f being coupled with the second terminal 832 of the integratorcapacitor 830 to the voltage source 810-e being coupled with the secondterminal 832 of the integrator capacitor 830. By connecting the secondterminal 832 of the integrator capacitor 830 to the voltage source at alower voltage, the charge stored by the integrator capacitor 830 may beshifted to a lower voltage, and accordingly the voltage of signal line280-c, coupled with the first terminal 831 of the integrator capacitor830, may drop by voltage level of V₅−V₄ (or just V₅ in the event thatvoltage source 810-e is coupled with a common ground point). Thus,deactivating switching component 820-f may initiate a second shiftingoperation for the integrator capacitor 830. In examples that do notemploy source following, this shifting may reduce the voltage of thesignal line 280-c to a level that may be read by the sense component130-d (e.g., a voltage between low and high voltage sources of the sensecomponent 130-d, not shown).

At 1018, the access procedure may include enabling the source followeramplifier 640-c for a second time. Connecting the source followeramplifier 640-c with the voltage source 810-g may support charge flowingthrough the source follower amplifier 640-c from the signal line 280-cto the source follower line 802, and also an amplified charge (e.g., amultiple of the charge flowing from the signal line 280-c) flowingthrough the source follower amplifier 640-c from the voltage source810-g to the source follower line 802. Accordingly, charge mayaccumulate on the source follower line 802 until the voltage thresholdof the transistor is no longer exceeded. In other words, the voltage ofthe source follower line 802 may rise to a level ofV_(SF)=(V_(sig)−V_(th)), where V_(th) is the threshold voltage of thetransistor of the source follower amplifier 640-c. In some examples thevoltage of the signal line 280-c may only drop by a negligible amountupon enabling the source follower amplifier 640-c, because only atrivial amount of charge flows from the signal line 280-c to the sourcefollower line 802. Although the voltage of the source follower line 802may be lower than the voltage of the signal line 280-c, the increasedamount of charge provided to the source follower line 802 may supportlarger components in the sense component 130-d, and may also limitcharge sharing between the signal line 280-c and the sense component130-d.

At 1019, the access procedure may include isolating the second node132-d of the sense component 130-d from the source follower line 802 bydeactivating switching component 820-h (e.g., by deactivating logicalsignal ISO₂). Isolating the sense component 130-c from the sourcefollower line 802 may allow the sense component 130-c to store (e.g.,“hold”) a reference voltage and/or charge associated with the sourcefollower line voltage at the second terminal 132-d of the sensecomponent 130-d prior to determining the logic state stored in thememory cell 105-d.

In some examples, the source follower load component 645-c may also beenabled during the operations of 1019. In examples where the sourcefollower load component 645-c is a transistor, signal EQA may again beenabled at the gate of the transistor, which may support current flowingthrough the source follower amplifier 640-c to also flow through thesource follower load component 645-c. Although signal EQA may be enabledor reenabled during source follower operations of 1019, signal EQA maybe disabled at other times (e.g., between 1008 and 1019, or afterdeveloping V_(ref,SF)), which may reduce energy consumption.

At 1020 the access procedure may include detecting a difference betweenthe stored voltages at the first and second terminals of the sensecomponent 130-d. which in the example of timing diagram 1000 may be theresult of a first and second selection of the same memory cell 105-d.For example, if the signal stored at the first terminal is greater thanthe signal stored at the second terminal (e.g.,V_(sig,SF,1)>V_(ref,SF)), the sense component 130-d may output a voltageequal to the high voltage source of the sense component. If the signalstored at the first terminal is less than the signal stored at thesecond terminal (e.g., V_(sig,SF,0)<V_(ref,SF)), the sense component130-d may output a voltage equal to the low voltage source of the sensecomponent.

Although illustrated as separate operations occurring at differenttimes, certain operations may occur simultaneously, or in a differentorder. In some examples, various operations may be advantageouslyinitiated simultaneously in order to reduce the amount of time requiredto sense a logic state of the memory cell 105-d. For example, connectingthe digit line 210-b with the signal line 280-b at 1002 may occur priorto the precharging at 1001, or these operations may occursimultaneously. Likewise, connecting the digit line 210-b with thesignal line 280-b at 1014 may occur prior to the precharging at 1013, orthese operations may occur simultaneously.

The order of operations shown in timing diagram 1000 is for illustrationonly, and various other orders and combinations of steps may beperformed to support self-boost in accordance with the presentdisclosure. Further, the timing of the operations of timing diagram 1000is also for illustration purposes only, and is not meant to indicate aparticular relative duration between one operation and another. Variousoperations may occur over a duration that is relatively shorter orrelatively longer than illustrated in various embodiments of self-boostin accordance with the present disclosure.

The transitions of the logical signals of the timing diagram 1000 areillustrative of transitions from one state to another, and generallyreflect transitions between an enabled or activated state (e.g., state“1”) and a disabled or deactivated state (e.g., state “0”) as associatedwith a particular numbered operation. In various examples the states maybe associated with a particular voltage of the logical signal (e.g., alogical input voltage applied to a gate of a transistor operating as aswitch), and the change in voltage from one state to another may not beinstantaneous. Rather, in some examples a voltage associated with alogical signal may follow a curve over time from one logical state toanother. Thus, the transitions shown in timing diagram 700 are notnecessarily indicative of an instantaneous transition. Further, theinitial state of a logical signal associated with a transition at anumbered operation may have been arrived during various times precedingthe numbered operation while still supporting the described transitionsand associated operations.

FIG. 11 shows a block diagram 1100 of a memory device 1105 that maysupport self-boost, source following, and sample-and-hold for accessingmemory cells in accordance with various embodiments of the presentdisclosure. Memory device 1105 may be referred to as an electronicmemory apparatus, and may be an example of a component of a memorydevice 100 as described with reference to FIG. 1.

Memory device 1105 may include one or more memory cells 1110, which maybe an example of memory cells 105 described with reference to FIGS. 1through 10. Memory device 1105 may also include a memory controller1115, a word line 1120, a plate line 1125, a reference component 1130, asense component 1135, an access line 1140, and a latch 1145. Thesecomponents may be in electronic communication with each other and mayperform one or more of the functions described herein. In some cases,memory controller 1115 may include biasing component 1150 and timingcomponent 1155.

Memory controller 1115 may be in electronic communication with word line1120, access line 1140, sense component 1135, and plate line 1125, whichmay be examples of word line 205, digit line 210, sense component 130,and plate line 215 described with reference to FIGS. 1 and 2. Accessline 1140 may also be an example of digit line 210-a and signal line280-a described with reference to FIG. 4, or an example of digit line210-b, signal line 280-b, and source follower signal line 602 describedwith reference to FIG. 6, or an example of digit line 210-c, signal line280-c, and source follower line 802 described with reference to FIG. 8.In some examples the memory device 1105 may also include referencecomponent 1130 and latch 1145. The components of memory array 1105 maybe in electronic communication with each other and may performembodiments of the functions described with reference to FIGS. 1 through10. In some cases, reference component 1130, sense component 1135, andlatch 1145 may be components of memory controller 1115.

In some examples, access line 1140 is in electronic communication withsense component 1135 and a ferroelectric capacitor of a memory cell1110. A memory cell 1110 may be writable with a logic state (e.g., afirst or second logic state). Word line 1120 may be in electroniccommunication with memory controller 1115 and a selection component ofmemory cell 1110. Plate line 1125 may be in electronic communicationwith memory controller 1115 and a plate of the ferroelectric capacitorof memory cell 1110. Sense component 1135 may be in electroniccommunication with memory controller 1115, access line 1140, latch 1145,and reference line 1160. Reference component 1130 may be in electroniccommunication with memory controller 1115 and reference line 1160. Someexamples may omit reference component 1130, and may generate a referencevia the memory cell 1110. In some examples, the access line 1140 mayprovide the functions of reference line 1160. Sense control line 1165may be in electronic communication with sense component 1135 and memorycontroller 1115. These components may also be in electroniccommunication with other components, both inside and outside of memorydevice 1105, in addition to components not listed above, via othercomponents, connections, or busses.

Memory controller 1115 may be configured to activate word line 1120,plate line 1125, or access line 1140 by applying voltages to thosevarious nodes. For example, biasing component 1150 may be configured toapply a voltage to operate memory cell 1110 to read or write memory cell1110 as described above. In some cases, memory controller 1115 mayinclude a row decoder, column decoder, or both, as described withreference to FIG. 1, which may enable memory controller 1115 to accessone or more memory cells 105. Biasing component 1150 may also providevoltage potentials to reference component 1130, or memory cell 1110, inorder to generate a reference signal for sense component 1135.Additionally, biasing component 1150 may provide voltage potentials forthe operation of sense component 1135.

In some cases, memory controller 1115 may perform its operations usingtiming component 1155. For example, timing component 1155 may controlthe timing of the various word line selections or plate biasing,including timing for switching and voltage application to perform thememory functions, such as reading and writing, discussed herein. In somecases, timing component 1155 may control the operations of biasingcomponent 1150.

Reference component 1130 may include various components to generate areference signal for sense component 1135. Reference component 1130 mayinclude circuitry configured to produce a reference signal. In somecases, reference component 1130 may be implemented using other memorycells 1110. Sense component 1135 may compare a signal from memory cell1110 (e.g., via access line 1140) with a reference signal from referencecomponent 1130, or from another signal from the access line 1140. Upondetermining the logic state, the sense component may then store theoutput in latch 1145, where it may be used in accordance with theoperations of an electronic device that includes the memory device 1105.Sense component 1135 may include a sense amplifier in electroniccommunication with the latch and the ferroelectric memory cell.

Memory controller 1115 may be an example of the memory controller 1215described with reference to FIG. 12.

Memory controller 1115 and/or at least some of its varioussub-components may be implemented in hardware, software executed by aprocessor, firmware, or any combination thereof. If implemented insoftware executed by a processor, the functions of the memory controller1115 and/or at least some of its various sub-components may be executedby a general-purpose processor, a digital signal processor (DSP), anapplication-specific integrated circuit (ASIC), an field-programmablegate array (FPGA) or other programmable logic device, discrete gate ortransistor logic, discrete hardware components, or any combinationthereof designed to perform the functions described in the presentdisclosure. The memory controller 1115 and/or at least some of itsvarious sub-components may be physically located at various positions,including being distributed such that portions of functions areimplemented at different physical locations by one or more physicaldevices. In some examples, memory controller 1115 and/or at least someof its various sub-components may be a separate and distinct componentin accordance with various embodiments of the present disclosure. Inother examples, memory controller 1115 and/or at least some of itsvarious sub-components may be combined with one or more other hardwarecomponents, including but not limited to an I/O component, atransceiver, a network server, another computing device, one or moreother components described in the present disclosure, or a combinationthereof in accordance with various embodiments of the presentdisclosure.

In some examples, the memory controller 1115, including anysubcomponents thereof, may apply a first voltage to a first node of acapacitor that is coupled to a first access line of a memory cell, applya second voltage to a second node of the capacitor, apply a thirdvoltage to the second node of the capacitor before selecting the memorycell for a sensing operation, select the memory cell for the sensingoperation, compare a resultant voltage of first access line to areference voltage at the sensing component, where the resultant voltageis based on applying the first voltage and the third voltage to thecapacitor and on selecting the memory cell for the sensing operation,and determine a logic value associated with the memory cell based oncomparing the resultant voltage and the reference voltage at the sensingcomponent.

In some examples the memory controller 1115, including any subcomponentsthereof, may develop a first voltage at an access line of a memorydevice that is coupled to an array side of a sensing component and areference side of the sensing component, the first voltage based on astate of charge of a memory cell of the memory device, isolate theaccess line of the memory device from the array side of the sensingcomponent to store a first read voltage of the sensing component that isbased on the first voltage, develop a second voltage at the access lineof the memory device, the second voltage based on a reference voltage ofthe memory device, and determine a logic value associated with thememory cell based on comparing the first read voltage and a second readvoltage that is based on the second voltage.

FIG. 12 shows a block diagram 1200 of a memory controller 1215 that maysupport self-boost, source following, and sample-and-hold for accessingmemory cells in accordance with various embodiments of the presentdisclosure. The memory controller 1215 may be an example of a memorycontroller 150 described with reference to FIG. 1. The memory controller1215 may include biasing component 1220, timing component 1225, voltageselector 1230, memory cell selector 1235, sense controller 1240, andamplifier selector 1245. Each of these modules may communicate, directlyor indirectly, with one another (e.g., via one or more buses).

Voltage selector 1230 may initiate the selection of voltage sources tosupport various access operations of a memory device. For example, thevoltage selector 1230 may generate logical signals used to activate ordeactivate various switching components, such as switching components420, 620, or 820 described with reference to FIGS. 4, 6, and 8. Thevoltage selector 1230 may generate one or more of the logical signals oftiming diagrams 500, 700, 900, or 1000 described with reference to FIGS.5, 7, 9, and 10.

For example, voltage selector 1230 may generate a signal to apply afirst voltage to a first node of a capacitor that is coupled with afirst access line of a memory cell, and apply a second voltage to asecond node of the capacitor. In some cases, applying the first voltageto the first node of the capacitor includes activating a switchingcomponent coupled between the first node of the capacitor and a firstvoltage source. The voltage selector 1230 may generate a signal todeactivate the switching component coupled between the first node of thecapacitor and the first voltage source prior to applying the thirdvoltage to the second node of the capacitor. In some cases the voltageselector 1230 may generate a signal to apply a third voltage to thesecond node of the capacitor before selecting the memory cell for asensing operation. In some cases, applying the third voltage to thesecond node of the capacitor includes activating a switching componentcoupled between the second node of the capacitor and the first voltagesource. In some examples the voltage selector 1230 may generate a signalto apply, after isolating the first node of the sense component, thefirst voltage to the first node of the capacitor and the second voltageto the second node of the capacitor. In some examples, the voltageselector 1230 may generate a signal to apply the second voltage to thesecond node of the capacitor after selecting the memory cell for thesensing operation. In some examples, the voltage selector 1230 maygenerate a signal to apply the third voltage to the second node of thecapacitor before selecting the memory cell for a second selectionoperation.

In some embodiments, the voltage selector 1230 may generate a signal toapply the second voltage and the third voltage to a node of anothercapacitor that is coupled to the sensing component, where a referencevoltage is based on applying the second voltage and the third voltage tothe node of the other capacitor. In some embodiments the voltageselector 1230 may generate a signal to apply a fourth voltage to anothernode of the other capacitor, where a reference voltage is based onapplying the fourth voltage to the other node of the other capacitor.

Memory cell selector 1235 may select a memory cell for sensingoperations. For example, the memory cell selector 1235 may generatelogical signals used to activate or deactivate a selection component,such as selection components 220 described with reference to FIG. 2. Thememory cell selector 1235 may generate the word line logical signals oftiming diagrams 500, 700, 900, or 1000 described with reference to FIGS.5, 7, 9, and 10. The memory cell selector 1235 may generate a signal todevelop a first voltage at an access line of a memory device that iscoupled to an array side of a sensing component, the first voltage basedon a state of charge of a memory cell of the memory device

In some examples the memory cell selector 1235 may generate a signal todevelop a second voltage at the access line of the memory device, thesecond voltage based on a reference voltage of the memory device. Insome examples the memory cell selector 1235 may generate a signal toapply a selection voltage to the second access line of the memory cellto select the memory cell for a second sensing operation, where areference voltage is based on selecting the memory cell for the secondsensing operation.

Sense controller 1240 may control various operations of a sensecomponent, such as sense components 130 described with reference toFIGS. 1, 2, 4, 6, and 8. For example, the sense controller 1240 maygenerate logical signals used to activate or deactivate an isolationcomponent, such as switching components 420, 620, and 820 described withreference to FIGS. 4, 6, and 8. The sense controller 1240 may generatethe ISO signals of timing diagrams 500, 700, 900, or 1000 described withreference to FIGS. 5, 7, 9, and 10.

For example, the sense controller 1240 may generate a signal to isolatean access line of a memory device from the array side of the sensingcomponent to store a first read voltage of the sensing component that isbased on a first voltage. In some examples the sense controller 1240 maygenerate a signal to isolate a first node of a sense component from thefirst access line before comparing the signal with a reference, to holda resultant voltage at the first node of the sense component while thereference voltage is generated.

In some embodiments the sense controller 1240 may compare a resultantvoltage of a first access line to a reference voltage at the sensingcomponent, where the resultant voltage is based on selecting the memorycell for the sensing operation. The sense controller 1240 may determinea logic value associated with the memory cell based on comparing theresultant voltage and the reference voltage at the sensing component, ordetermine a logic value associated with the memory cell based oncomparing a first read voltage and a second read voltage.

Amplifier selector 1245 may initiate the selection of amplifiers tosupport various access operations of a memory device. For example, theamplifier selector 1245 may generate logical signals used to activate ordeactivate various switching components, such as switching components420, 620, or 820 described with reference to FIGS. 4, 6, and 8. Theamplifier selector 1245 may generate one or more of the logical signalsof timing diagrams 500, 700, 900, or 1000 described with reference toFIGS. 5, 7, 9, and 10.

For example, the amplifier selector 1245 may generate a signal to enablean amplifier coupled between a memory cell and a sense component on afirst access line, where a resultant voltage of the first access line isbased on enabling the amplifier. In some examples the amplifier selector1245 may generate a signal to enable the amplifier for a second time,where a reference voltage is based on selecting the memory cell for thesecond sensing operation and enabling the amplifier for the second time.In some examples the amplifier selector 1245 may generate a signal toenable a first amplifier on the first access line that is coupledbetween the memory cell and the sense component, where a resultantvoltage of first access line is based on enabling the first amplifier,and enable a second amplifier that is coupled between a referencevoltage source and the sense component where a reference voltage isbased on enabling the second amplifier.

FIG. 13 shows a diagram of a system 1300 including a device 1305 thatmay support self-boost, source following, and sample-and-hold foraccessing memory cells in accordance with various embodiments of thepresent disclosure. Device 1305 may be an example of or include thecomponents of memory device 100 as described above, e.g., with referenceto FIG. 1. Device 1305 may include components for bi-directionalcommunications including components for transmitting and receivingcommunications, including memory controller 1315, memory cells 1320,basic input/output system (BIOS) component 1325, processor 1330, I/Ocontroller 1335, and peripheral components 1340. These components may bein electronic communication via one or more busses (e.g., bus 1310).

Memory controller 1315 may operate one or more memory cells as describedherein. Specifically, memory controller 1315 may be configured tosupport self-boost, source following, and sample-and-hold for accessingmemory cells. In some cases, memory controller 1315 may include a rowdecoder, column decoder, or both, as described with reference to FIG. 1(not shown).

Memory cells 1320 may be an example of memory cells 105 or 1110described with reference to FIGS. 1 through 11, and may storeinformation (i.e., in the form of a logical state) as described herein.

BIOS component 1325 be a software component that includes BIOS operatedas firmware, which may initialize and run various hardware components.BIOS component 1325 may also manage data flow between a processor andvarious other components, e.g., peripheral components, input/outputcontrol component, etc. BIOS component 1325 may include a program orsoftware stored in read only memory (ROM), flash memory, or any othernon-volatile memory.

Processor 1330 may include an intelligent hardware device, (e.g., ageneral-purpose processor, a DSP, a central processing unit (CPU), amicrocontroller, an ASIC, an FPGA, a programmable logic device, adiscrete gate or transistor logic component, a discrete hardwarecomponent, or any combination thereof). In some cases, processor 1330may be configured to operate a memory array using a memory controller.In other cases, a memory controller may be integrated into processor1330. Processor 1330 may be configured to execute computer-readableinstructions stored in a memory to perform various functions (e.g.,functions or tasks supporting self-boost, source following, andsample-and-hold for accessing memory cells).

I/O controller 1335 may manage input and output signals for device 1305.I/O controller 1335 may also manage peripherals not integrated intodevice 1305. In some cases, I/O controller 1335 may represent a physicalconnection or port to an external peripheral. In some cases, I/Ocontroller 1335 may utilize an operating system such as iOS®, ANDROID®,MS-DOS®, MS-WINDOWS®, OS/2®, UNIX®, LINUX®, or another known operatingsystem. In other cases, I/O controller 1335 may represent or interactwith a modem, a keyboard, a mouse, a touchscreen, or a similar device.In some cases, I/O controller 1335 may be implemented as part of aprocessor. In some cases, a user may interact with device 1305 via I/Ocontroller 1335 or via hardware components controlled by I/O controller1335.

Peripheral components 1340 may include any input or output device, or aninterface for such devices. Examples may include disk controllers, soundcontroller, graphics controller, Ethernet controller, modem, universalserial bus (USB) controller, a serial or parallel port, or peripheralcard slots, such as peripheral component interconnect (PCI) oraccelerated graphics port (AGP) slots.

Input 1345 may represent a device or signal external to device 1305 thatprovides input to device 1305 or its components. This may include a userinterface or an interface with or between other devices. In some cases,input 1345 may be managed by I/O controller 1335, and may interact withdevice 1305 via a peripheral component 1340.

Output 1350 may represent a device or signal external to device 1305configured to receive output from device 1305 or any of its components.Examples of output 1350 may include a display, audio speakers, aprinting device, another processor or printed circuit board, etc. Insome cases, output 1350 may be a peripheral element that interfaces withdevice 1305 via peripheral component(s) 1340. In some cases, output 1350may be managed by I/O controller 1335.

The components of device 1305 may include circuitry designed to carryout their functions. This may include various circuit elements, forexample, conductive lines, transistors, capacitors, inductors,resistors, amplifiers, or other active or inactive elements, configuredto carry out the functions described herein. Device 1305 may be acomputer, a server, a laptop computer, a notebook computer, a tabletcomputer, a mobile phone, a wearable electronic device, a personalelectronic device, or the like. Or device 1305 may be a portion oraspect of such a device.

FIG. 14 shows a flowchart illustrating a method 1400 that may supportself-boost, source following, and sample-and-hold for accessing memorycells in accordance with various embodiments of the present disclosure.The operations of method 1400 may be implemented by a memory device 100,a device 1105, a device 1305, or its components as described herein. Forexample, the operations of method 1400 may be performed by a memorycontroller as described with reference to FIGS. 1 through 13. In someexamples, a memory device may execute a set of codes to control thefunctional elements of the device to perform the functions describedbelow. Additionally or alternatively, the memory device may perform someor all of the functions described below using special-purpose hardware.

At block 1405 the memory device may apply a first voltage to a firstnode of a capacitor that is coupled to a first access line of a memorycell. In some examples, applying the first voltage to the first node ofthe capacitor may include activating a switching component coupledbetween the first node of the capacitor and a first voltage source. Theoperations of block 1405 may be performed according to the methodsdescribed with reference to FIGS. 4 through 10. In certain examples,some or all of the operations of block 1405 may be performed by avoltage selector 1230 as described with reference to FIG. 12.

At block 1410 the memory device may apply a second voltage to a secondnode of the capacitor. The operations of block 1410 may be performedaccording to the methods described with reference to FIGS. 4 through 10.In certain examples, some or all of the operations of block 1410 may beperformed by a voltage selector 1230 as described with reference to FIG.12.

At block 1415 the memory device may apply a third voltage to the secondnode of the capacitor before selecting the memory cell for a sensingoperation. Some examples may include deactivating the switchingcomponent coupled between the first node of the capacitor and the firstvoltage source prior to applying the third voltage to the second node ofthe capacitor. In some cases, applying the third voltage to the secondnode of the capacitor includes activating a switching component coupledbetween the second node of the capacitor and the first voltage source.The operations of block 1415 may be performed according to the methodsdescribed with reference to FIGS. 4 through 10. In certain examples,some or all of the operations of block 1415 may be performed by avoltage selector 1230 as described with reference to FIG. 12.

At block 1420 the memory device may select the memory cell for thesensing operation. In some cases, the method may also include enablingan amplifier coupled between the memory cell and the sense component onthe first access line, which may include activating a switchingcomponent coupled between the amplifier and a voltage source. Theoperations of block 1420 may be performed according to the methodsdescribed with reference to FIGS. 4 through 10. In certain examples,some or all of the operations of block 1420 may be performed by a memorycell selector 1235 as described with reference to FIG. 12.

At block 1425 the memory device may compare a resultant voltage of firstaccess line to a reference voltage at the sensing component, wherein theresultant voltage is based at least in part on applying the firstvoltage and the third voltage to the capacitor and on selecting thememory cell for the sensing operation. The operations of block 1425 maybe performed according to the methods described with reference to FIGS.4 through 10. In certain examples, some or all of the operations ofblock 1425 may be performed by a sense controller 1240 as described withreference to FIG. 12.

At block 1430 the memory device may determine a logic value associatedwith the memory cell based at least in part on comparing the resultantvoltage and the reference voltage at the sensing component. Theoperations of block 1430 may be performed according to the methodsdescribed with reference to FIGS. 4 through 10. In certain examples,some or all of the operations of block 1430 may be performed by a sensecontroller 1240 as described with reference to FIG. 12.

FIG. 15 shows a flowchart illustrating a method 1500 that may supportsample-and-hold for accessing memory cells in accordance with variousembodiments of the present disclosure. The operations of method 1500 maybe implemented by a memory device 100, a device 1105, a device 1305, orits components as described herein. For example, the operations ofmethod 1500 may be performed by a memory controller as described withreference to FIG. 1, 11, or 13. In some examples, a memory device mayexecute a set of codes to control the functional elements of the deviceto perform the functions described below. Additionally or alternatively,the memory device may perform some or all of the functions describedbelow using special-purpose hardware.

At block 1505 the memory device may develop a first voltage at an accessline of a memory device that is coupled to an array side of a sensingcomponent and a reference side of the sensing component, the firstvoltage based at least in part on a state of charge of a memory cell ofthe memory device. The operations of block 1505 may be performedaccording to the methods described with reference to FIGS. 4 through 10.In certain examples, some or all of the operations of block 1505 may beperformed by a voltage selector 1230 as described with reference to FIG.12.

At block 1510 the memory device may isolate the access line of thememory device from the array side of the sensing component to store afirst read voltage of the sensing component that is based at least inpart on the first voltage. The operations of block 1510 may be performedaccording to the methods described with reference to FIGS. 4 through 10.In certain examples, some or all of the operations of block 1510 may beperformed by a sense controller 1240 as described with reference to FIG.12.

At block 1515 the memory device may develop a second voltage at theaccess line of the memory device, the second voltage based at least inpart on a reference voltage of the memory device. The operations ofblock 1515 may be performed according to the methods described withreference to FIGS. 4 through 10. In certain examples, some or all of theoperations of block 1515 may be performed by a voltage selector 1230 asdescribed with reference to FIG. 12.

At block 1520 the memory device may determine a logic value associatedwith the memory cell based at least in part on comparing the first readvoltage and a second read voltage that is based at least in part on thesecond voltage. The operations of block 1520 may be performed accordingto the methods described with reference to FIGS. 4 through 10. Incertain examples, some or all of the operations of block 1520 may beperformed by a sense controller 1240 as described with reference to FIG.12.

It should be noted that the methods described above describe possibleimplementations, and that the operations and the steps may be rearrangedor otherwise modified and that other implementations are possible.Furthermore, embodiments from two or more of the methods may becombined.

The description herein provides examples, and is not limiting of thescope, applicability, or examples set forth in the claims. Changes maybe made in the function and arrangement of elements discussed withoutdeparting from the scope of the disclosure. Various examples may omit,substitute, or add various procedures or components as appropriate.Also, features described with respect to some examples may be combinedin other examples.

As used herein, the term “virtual ground” refers to a node of anelectrical circuit that is held at a voltage of approximately zero volts(0V), or more generally represents a reference voltage of the electricalcircuit or device including the electrical circuit, which may or may notbe directly coupled with ground. Accordingly, the voltage of a virtualground may temporarily fluctuate and return to approximately 0V, orvirtual 0V, at steady state. A virtual ground may be implemented usingvarious electronic circuit elements, such as a voltage dividerconsisting of operational amplifiers and resistors. Otherimplementations are also possible. “Virtual grounding” or “virtuallygrounded” means connected to approximately 0V.

The term “electronic communication” and “coupled” refers to arelationship between components that supports electron flow between thecomponents. This may include a direct connection or coupling betweencomponents or may include intermediate components. In other words,components that are “connected with” or “coupled with” are in electroniccommunication with each other. Components in electronic communicationmay be actively exchanging electrons or signals (e.g., in an energizedcircuit) or may not be actively exchanging electrons or signals (e.g.,in a de-energized circuit) but may be configured and operable toexchange electrons or signals upon a circuit being energized. By way ofexample, two components physically connected or coupled via a switch(e.g., a transistor) are in electronic communication regardless of thestate of the switch (i.e., open or closed).

The term “isolated” refers to a relationship between components in whichelectrons are not presently capable of flowing between them; componentsare isolated from each other if there is an open circuit between them.For example, two components physically coupled by a switch may beisolated from each other when the switch is open.

As used herein, the term “shorting” refers to a relationship betweencomponents in which a conductive path is established between thecomponents via the activation of a single intermediary component betweenthe two components in question. For example, a first component shortedto a second component may exchange electrons with the second componentwhen a switch between the two components is closed. Thus, shorting maybe a dynamic operation that enables the application of voltage and/orflow of charge between components (or lines) that are in electroniccommunication.

The devices discussed herein, including memory device 100, may be formedon a semiconductor substrate, such as silicon, germanium,silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In somecases, the substrate is a semiconductor wafer. In other cases, thesubstrate may be a silicon-on-insulator (SOI) substrate, such assilicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layersof semiconductor materials on another substrate. The conductivity of thesubstrate, or sub-regions of the substrate, may be controlled throughdoping using various chemical species including, but not limited to,phosphorous, boron, or arsenic. Doping may be performed during theinitial formation or growth of the substrate, by ion-implantation, or byany other doping means.

A transistor or transistors discussed herein may represent afield-effect transistor (FET) and comprise a three terminal deviceincluding a source, drain, and gate. The terminals may be coupled withother electronic elements through conductive materials, e.g., metals.The source and drain may be conductive and may comprise a heavily-doped,e.g., degenerate, semiconductor region. The source and drain may beseparated by a lightly-doped semiconductor region or channel. If thechannel is n-type (i.e., majority carriers are electrons), then the FETmay be referred to as a n-type FET. If the channel is p-type (i.e.,majority carriers are holes), then the FET may be referred to as ap-type FET. The channel may be capped by an insulating gate oxide. Thechannel conductivity may be controlled by applying a voltage to thegate. For example, applying a positive voltage or negative voltage to ann-type FET or a p-type FET, respectively, may result in the channelbecoming conductive. A transistor may be “on” or “activated” when avoltage greater than or equal to the transistor's threshold voltage isapplied to the transistor gate. The transistor may be “off” or“deactivated” when a voltage less than the transistor's thresholdvoltage is applied to the transistor gate.

The description set forth herein, in connection with the appendeddrawings, describes example configurations and does not represent allthe examples that may be implemented or that are within the scope of theclaims. The terms “example,” “exemplary,” and “embodiment,” as usedherein mean “serving as an example, instance, or illustration,” and not“preferred” or “advantageous over other examples.” The detaileddescription includes specific details for the purpose of providing anunderstanding of the described techniques. These techniques, however,may be practiced without these specific details. In some instances,well-known structures and devices are shown in block diagram form inorder to avoid obscuring the concepts of the described examples.

In the appended figures, similar components or features may have thesame reference label. Further, various components of the same type maybe distinguished by following the reference label by a dash and a secondlabel that distinguishes among the similar components. If just the firstreference label is used in the specification, the description isapplicable to any one of the similar components having the same firstreference label irrespective of the second reference label.

Information and signals described herein may be represented using any ofa variety of different technologies and techniques. For example, data,instructions, commands, information, signals, bits, symbols, and chipsthat may be referenced throughout the above description may berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, or any combinationthereof. Some drawings may illustrate signals as a single signal;however, it will be understood by a person of ordinary skill in the artthat the signal may represent a bus of signals, where the bus may have avariety of bit widths.

The various illustrative blocks, components, and modules described inconnection with the disclosure herein may be implemented or performedwith a general-purpose processor, a DSP, an ASIC, an FPGA or otherprogrammable logic device, discrete gate or transistor logic, discretehardware components, or any combination thereof designed to perform thefunctions described herein. A general-purpose processor may be amicroprocessor, but in the alternative, the processor may be anyconventional processor, controller, microcontroller, or state machine. Aprocessor may also be implemented as a combination of computing devices(e.g., a combination of a DSP and a microprocessor, multiplemicroprocessors, one or more microprocessors in conjunction with a DSPcore, or any other such configuration).

The functions described herein may be implemented in hardware, softwareexecuted by a processor, firmware, or any combination thereof. Ifimplemented in software executed by a processor, the functions may bestored on or transmitted over as one or more instructions or code on acomputer-readable medium. Other examples and implementations are withinthe scope of the disclosure and appended claims. For example, due to thenature of software, functions described above can be implemented usingsoftware executed by a processor, hardware, firmware, hardwiring, orcombinations of any of these. Features implementing functions may alsobe physically located at various positions, including being distributedsuch that portions of functions are implemented at different physicallocations. Also, as used herein, including in the claims, “or” as usedin a list of items (for example, a list of items prefaced by a phrasesuch as “at least one of” or “one or more of”) indicates an inclusivelist such that, for example, a list of at least one of A, B, or C meansA or B or C or AB or AC or BC or ABC (i.e., A and B and C).

As used herein, the term “substantially” means that the modifiedcharacteristic (e.g., a verb or adjective modified by the termsubstantially) need not be absolute but is close enough so as to achievethe advantages of the characteristic.

As used herein, the phrase “based on” shall not be construed as areference to a closed set of conditions. For example, an exemplary stepthat is described as “based on condition A” may be based on both acondition A and a condition B without departing from the scope of thepresent disclosure. In other words, as used herein, the phrase “basedon” shall be construed in the same manner as the phrase “based at leastin part on.”

Computer-readable media includes both non-transitory computer storagemedia and communication media including any medium that facilitatestransfer of a computer program from one place to another. Anon-transitory storage medium may be any available medium that can beaccessed by a general purpose or special purpose computer. By way ofexample, and not limitation, non-transitory computer-readable media cancomprise RAM, ROM, electrically erasable programmable read only memory(EEPROM), compact disk (CD) ROM or other optical disk storage, magneticdisk storage or other magnetic storage devices, or any othernon-transitory medium that can be used to carry or store desired programcode means in the form of instructions or data structures and that canbe accessed by a general-purpose or special-purpose computer, or ageneral-purpose or special-purpose processor. Also, any connection isproperly termed a computer-readable medium. For example, if the softwareis transmitted from a website, server, or other remote source using acoaxial cable, fiber optic cable, twisted pair, digital subscriber line(DSL), or wireless technologies such as infrared, radio, and microwave,then the coaxial cable, fiber optic cable, twisted pair, digitalsubscriber line (DSL), or wireless technologies such as infrared, radio,and microwave are included in the definition of medium. Disk and disc,as used herein, include CD, laser disc, optical disc, digital versatiledisc (DVD), floppy disk and Blu-ray disc where disks usually reproducedata magnetically, while discs reproduce data optically with lasers.Combinations of the above are also included within the scope ofcomputer-readable media.

The description herein is provided to enable a person skilled in the artto make or use the disclosure. Various modifications to the disclosurewill be readily apparent to those skilled in the art, and the genericprinciples defined herein may be applied to other variations withoutdeparting from the scope of the disclosure. Thus, the disclosure is notto be limited to the examples and designs described herein but is to beaccorded the broadest scope consistent with the principles and novelfeatures disclosed herein.

What is claimed is:
 1. An electronic memory apparatus, comprising: amemory cell coupled between a first access line and a second accessline; a capacitor, separate from the memory cell, coupled between thefirst access line and a first voltage source; a second voltage sourcecoupled with the first access line via a first switching component; anda sensing component coupled with the first access line at a firstterminal of the sensing component and coupled with a reference voltagesource at a second terminal of the sensing component, the sensingcomponent configured to detect a logic state stored by the memory cellbased at least in part on a flow of charge between the capacitor and thefirst access line.
 2. The electronic memory apparatus of claim 1,further comprising: an amplifier coupled between the capacitor and thesensing component.
 3. The electronic memory apparatus of claim 2,wherein the amplifier is coupled with the second voltage source via asecond switching component.
 4. The electronic memory apparatus of claim1, further comprising: a reference line coupled between the referencevoltage source and the sensing component; and another capacitor,separate from the memory cell, coupled between the reference line andthe first voltage source, wherein the sensing component is configured todetect the logic state stored by the memory cell based at least in parton a flow of charge between the other capacitor and the reference line.5. The electronic memory apparatus of claim 4, wherein the referencevoltage source is coupled with the reference line via a third switchingcomponent.
 6. The electronic memory apparatus of claim 4, furthercomprising: an amplifier coupled between the capacitor and the sensingcomponent another amplifier coupled between the other capacitor and thesensing component.
 7. The electronic memory apparatus of claim 6,wherein: the amplifier is coupled with the second voltage source via asecond switching component; and the other amplifier is coupled with thesecond voltage source via a fourth switching component.
 8. Theelectronic memory apparatus of claim 1, wherein the second terminal ofthe sensing component is coupled with the first access line, and theelectronic memory apparatus comprises: a first isolation componentcoupled between the first terminal of the sensing component and thefirst access line, the first isolation component operable to, aftergenerating a first sense voltage at the first terminal of the sensingcomponent, isolate the first terminal of the sensing component from thefirst access line during a generation of a reference voltage on thefirst access line.
 9. The electronic memory apparatus of claim 8,further comprising: a second isolation component coupled between thesecond terminal of the sensing component and the first access line. 10.A method, comprising: applying a first voltage to a first terminal of acapacitor, separate from a memory cell, that is coupled with a firstaccess line of the memory cell; applying a second voltage to a secondterminal of the capacitor; applying a third voltage to the secondterminal of the capacitor before selecting the memory cell for a sensingoperation; selecting the memory cell for the sensing operation;comparing a resultant voltage of first access line to a referencevoltage at the sensing component, wherein the resultant voltage is basedat least in part on selecting the memory cell for the sensing operationand on a flow of charge between the capacitor and the first access linethat is based at least in part on applying the first voltage and thethird voltage to the capacitor; and determining a logic value associatedwith the memory cell based at least in part on comparing the resultantvoltage and the reference voltage at the sensing component.
 11. Themethod of claim 10, wherein applying the first voltage to the firstterminal of the capacitor comprises: activating a switching componentcoupled between the first terminal of the capacitor and a first voltagesource.
 12. The method of claim 11, further comprising: deactivating theswitching component coupled between the first terminal of the capacitorand the first voltage source prior to applying the third voltage to thesecond terminal of the capacitor.
 13. The method of claim 11, whereinapplying the third voltage to the second terminal of the capacitorcomprises: activating a switching component coupled between the secondterminal of the capacitor and the first voltage source.
 14. The methodof claim 10, further comprising: applying the second voltage to thesecond terminal of the capacitor after selecting the memory cell for thesensing operation.
 15. The method of claim 10, further comprising:applying the second voltage and the third voltage to a terminal ofanother capacitor, separate from the memory cell, that is coupled withthe sensing component, wherein the reference voltage is based at leastin part on applying the second voltage and the third voltage to theterminal of the other capacitor.
 16. The method of claim 15, furthercomprising: applying a fourth voltage to another terminal of the othercapacitor, wherein the reference voltage is based at least in part onapplying the fourth voltage to the other terminal of the othercapacitor.
 17. The method of claim 15, further comprising: enabling afirst amplifier on the first access line that is coupled between thememory cell and the sense component, wherein the resultant voltage offirst access line is based at least in part on enabling the firstamplifier; and enabling a second amplifier that is coupled between areference voltage source and the sense component wherein the referencevoltage is based at least in part on enabling the second amplifier. 18.The method of claim 10, further comprising: enabling an amplifiercoupled between the memory cell and the sense component on the firstaccess line, wherein the resultant voltage of first access line is basedat least in part on enabling the amplifier.
 19. The method of claim 18,wherein enabling the amplifier coupled between the first access line andthe sense component comprises: activating a switching component coupledbetween the amplifier and a voltage source.
 20. The method of claim 18,further comprising: isolating a first terminal of the sense componentfrom the first access line before the comparing to hold the resultantvoltage at the first terminal of the sense component while the referencevoltage is generated.
 21. The method of claim 20, further comprising:applying, after isolating the first terminal of the sense component, thefirst voltage to the first terminal of the capacitor and the secondvoltage to the second terminal of the capacitor; applying the thirdvoltage to the second terminal of the capacitor before selecting thememory cell for a second selection operation; selecting the memory cellfor the second sensing operation; and enabling the amplifier for asecond time, wherein the reference voltage is based at least in part onselecting the memory cell for the second sensing operation and enablingthe amplifier for the second time.
 22. The method of claim 10, furthercomprising: isolating a first terminal of the sense component from thefirst access line before the comparing to hold the resultant voltage atthe first terminal of the sense component while the reference voltage isgenerated.
 23. The method of claim 22, further comprising: applying,after isolating the first terminal of the sense component, the firstvoltage to the first terminal of the capacitor and the second voltage tothe second terminal of the capacitor; applying the third voltage to thesecond terminal of the capacitor before selecting the memory cell for asecond selection operation; and applying the selection voltage to thesecond access line of the memory cell to select the memory cell for thesecond sensing operation, wherein the reference voltage is based atleast in part on selecting the memory cell for the second sensingoperation.
 24. The electronic memory apparatus of claim 9, furthercomprising: an amplifier coupled between the capacitor and both thefirst isolation component and the second isolation component.
 25. Theelectronic memory apparatus of claim 24, wherein the amplifier iscoupled with the second voltage source via a second switching component.